Inventor

POECHMUELLER PETER

DE65 patents

⚠️ This page may combine multiple inventors who share the name “POECHMUELLER PETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POECHMUELLER PETER

INFINEON TECHNOLOGIES AG

Methods for repairing and for operating a memory component

Self-refresh system and method for dynamic random access memory

Integrated memory circuit

Concept for a secure data communication between electronic devices

Method and system for manufacturing DRAMs with reduced self-refresh current requirements

Memory module with a heat dissipation means

Semiconductor memory configuration with a built-in-self-test

System for testing fast synchronous semiconductor circuits

Memory circuit comprising redundant memory areas

Memory module having memory chips protected from excessive heat

Method and device for reading and for checking the time position of data response signals read out from a memory module to be tested

Integrated memory and method for operating an integrated memory

System for testing fast integrated digital circuits, in particular semiconductor memory modules

Configuration for carrying out burn-in processing operations of semiconductor devices at wafer level

Integrated memory having memory cells with a magnetoresistive storage property

Integrated memory having memory cells and reference cells

Integrated dynamic semiconductor memory having redundant units of memory cells, and a method of self-repair

Circuit configuration for repairing a semiconductor memory

Controlled substrate voltage for memory switches

Automated layout transformation system and method

Testing device for testing a memory

Method for preventing electromigration in an MRAM

Integrated memory having memory cells with a magnetoresistive storage property and method of operating such a memory

Method and configuration for compensating for parasitic current losses

MRAM configuration

Configuration for testing chips using a printed circuit board

Method of testing memory cells with a hysteresis curve

Circuit configuration for regulating the power consumption of an integrated circuit

Integrated memory with at least two plate segments

Integrated memory having memory cells and reference cells

Test circuit for testing a synchronous memory circuit

Test circuit for testing a circuit

Integrated memory circuit and method for repairing a single bit error

Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose

Memory component and addressing of memory cells

Method and circuit arrangement for testing electrical modules

Circuit and method for generating an output signal

Semiconductor device with test circuit disconnected from power supply connection

Apparatus and method for calibrating signals

Backside of chip implementation of redundancy fuses and contact pads

Integrated dynamic memory, and method for operating the integrated dynamic memory

Method for recognizing and replacing defective memory cells in a memory

Integrated clock generator, particularly for driving a semiconductor memory with a test signal

Configuration and method for producing test signals for testing a multiplicity of semiconductor chips

Integrated memory and memory configuration with a plurality of memories and method of operating such a memory configuration

SIEMENS AG

Flexible fuse placement in redundant semiconductor memory

OCD with low output capacitance

Integrated circuit with improved off chip drivers

(unassigned)

Test circuit

INFINEON TECHOLOGIES AG

Test configuration and test method for testing a plurality of integrated circuits in parallel