Integrated memory circuit and method for repairing a single bit error

Abstract

The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information, an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information. The test unit comprises a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array, a read-out unit which reads out data stored in the memory area, a modification unit in order to modify the bits of the read-out data in such a way that the position of each bit changes and each of the bits is inverted in order to provide the second test data, which are subsequently written to the memory area with the aid of the write unit, and a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result.

1. An integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and comprising:
 a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising:
 an error memory for storing an item of repair information; and 
 an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and 
 
 a test unit for determining the repair information, the test unit comprising:
 a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array; 
 a read-out unit which reads out data stored in the memory area; 
 a modification unit in order to modify the bits of the read-out data to provide the second test data, which are subsequently written to the memory area by the write unit, and 
 a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result. 
 
 
   
   
     2. The integrated memory circuit of  claim 1 , further comprising: a test data provision unit being provided in order to provide the first test data as a bit sequence. 
   
   
     3. The integrated memory circuit of  claim 2 , wherein the test data provision unit provides the first test data as a bit sequence of identical logic states, and wherein the expected data provided to the comparator unit corresponds to inverted first test data. 
   
   
     4. The integrated memory circuit of  claim 2 , wherein the test unit is configured to determine repair information for different memory cells up to a predefined maximum number of memory cells. 
   
   
     5. The integrated memory circuit of  claim 1 , wherein the comparator unit modifies the read-out data in such a way that the position of each bit changes and each of the bits is inverted. 
   
   
     6. An integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, comprising:
 a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising:
 an error memory for storing an item of repair information; 
 an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area; and 
 
 a test unit for determining the repair information, the test unit comprising:
 a write unit, which successively writes first test data and second test data to a plurality of memory cells of a memory area of the memory cell array; 
 a read-out unit which reads out data stored in the memory area; 
 a comparator unit in order to compare the data read out after the writing of the second test data with expected data and to provide the repair information depending on the comparison result; 
 an interface unit in order to receive the first and second test data externally from the outside and to transmit the read-out data externally; and 
 an expected data provision unit in order to provide the expected data. 
 
 
   
   
     7. The memory circuit of  claim 6 , wherein the repair circuit further comprises a programming circuit for writing to the error memory depending on the repair information. 
   
   
     8. The memory circuit of  claim 6 , wherein the test unit is configured to determine repair information for different memory cells up to a predefined maximum number of memory cells. 
   
   
     9. The memory circuit of  claim 6 , wherein the error memory is a permanent memory that stores the stored information independently of a presence of a supply voltage. 
   
   
     10. The memory circuit of  claim 9 , wherein the permanent memory comprises an electrical fuse. 
   
   
     11. A method for repairing a single bit error in an integrated memory circuit having a memory cell array, comprising:
 writing first test data to a memory area of the integrated memory circuit; 
 reading out the data from the memory area; 
 modifying the read-out data by inverting the data bits of the memory area and changing the data bits in terms of their respective positions; 
 writing the modified data to the memory area; 
 reading out the modified data from the memory area; 
 comparing the read out modified data with expected data; and 
 providing the repair information depending on a result of the comparison. 
 
   
   
     12. The method of  claim 11 , wherein the first test data is selected as a sequence of bits having identical logic states, and the expected data corresponds to the first test data. 
   
   
     13. The method of  claim 11 , wherein the repair information is permanently stored. 
   
   
     14. The method of  claim 11 , wherein one of a memory area of the memory cell array and a redundancy memory area is accessed when accessing an address of the memory cell array, depending on the repair information. 
   
   
     15. The method of  claim 11 , wherein the modifying is done by the integrated memory circuit. 
   
   
     16. The method of  claim 11 , wherein the modifying is done a device external to the integrated memory circuit.