Inventor
KANARSKY THOMAS S
US21 patents
Patents
21 patentsUS7041538B2May 9, 2006
Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS
IBM124 citations99
US7250658B2Jul 31, 2007
Hybrid planar and FinFET CMOS devices
IBM164 citations98
US6911383B2Jun 28, 2005
Hybrid planar and finFET CMOS devices
IBM109 citations98
US6846734B2Jan 25, 2005
Method and process to make multiple-threshold metal gates CMOS technology
IBM105 citations95
US6333533B1Dec 25, 2001
Trench storage DRAM cell with vertical three-sided transfer device
IBM20 citations93
US6207493B1Mar 27, 2001
Formation of out-diffused bitline by laser anneal
IBM16 citations93
US7968915B2Jun 28, 2011
Dual stress memorization technique for CMOS application
IBM17 citations92
US7173312B2Feb 6, 2007
Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
IBM20 citations92
US7018891B2Mar 28, 2006
Ultra-thin Si channel CMOS with improved series resistance
IBM26 citations92
US6914303B2Jul 5, 2005
Ultra thin channel MOSFET
IBM33 citations92
US6677646B2Jan 13, 2004
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
IBM41 citations92
US5536388AJul 16, 1996
Vertical electroetch tool nozzle and method
IBM42 citations91
US7989298B1Aug 2, 2011
Transistor having V-shaped embedded stressor
IBM27 citations90
US7834399B2Nov 16, 2010
Dual stress memorization technique for CMOS application
IBM15 citations84
US7314789B2Jan 1, 2008
Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification
IBM13 citations84
US6905941B2Jun 14, 2005
Structure and method to fabricate ultra-thin Si channel devices
IBM13 citations84
US5620611AApr 15, 1997
Method to improve uniformity and reduce excess undercuts during chemical etching in the manufacture of solder pads
IBM16 citations81
US6258661B1Jul 10, 2001
Formation of out-diffused bitline by laser anneal
IBM7 citations74
US7871893B2Jan 18, 2011
Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices
IBM4 citations63
US7211490B2May 1, 2007
Ultra thin channel MOSFET
IBM2 citations63
US6376873B1Apr 23, 2002
Vertical DRAM cell with robust gate-to-storage node isolation
IBM6 citations63