Inventor

KIM JIN-KI

CA211 patents

⚠️ This page may combine multiple inventors who share the name “KIM JIN-KI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM JIN-KI

MOSAID TECHNOLOGIES INC

Partial block erase architecture for flash memory

Multiple independent serial link memory

Flash multi-level threshold distribution scheme

Non-volatile semiconductor memory with page erase

Memory with output control

Low power content addressable memory architecture

Non-volatile memory device having configurable page size

Flash memory program inhibit scheme

Composite memory having a bridging device for connecting discrete memory devices to a system

NAND flash memory having multiple cell substrates

Stacked semiconductor devices including a master device

Non-volatile memory with dynamic multi-mode operation

Non-volatile semiconductor memory having multiple external power supplies

Differential sensing amplifier for content addressable memory

Memory with output control

Memory with output control

Non-volatile memory with dynamic multi-mode operation

Method and system for accessing a flash memory device

Hierarchical common source line structure in NAND flash memory

Source side asymmetrical precharge programming scheme

System and method of operating memory devices of mixed type

Apparatus and method of page program operation for memory devices with mirror back-up of data

Modular command structure for memory and memory system

Memory with output control

Non-volatile memory serial core architecture

Apparatus and method of page program operation for memory devices with mirror back-up of data

Flash memory program inhibit scheme

Hybrid solid-state memory system having volatile and non-volatile memory

Flash memory program inhibit scheme

KIM JIN-KI

Non-volatile memory device having configurable page size

NAND flash memory having multiple cell substrates

Scalable memory system

Multipage program scheme for flash memory

Flexible memory operations in NAND flash devices

Source side asymmetrical precharge programming scheme

Non-volatile memory bank and page buffer therefor

Non-volatile semiconductor memory having multiple external power supplies

Bridge device architecture for connecting discrete memory devices to a system

Flexible memory operations in NAND flash devices

SAMSUNG ELECTRONICS CO LTD

Nonvolatile semiconductor memory device and an optimizing programming method thereof

Integrated circuit memory devices having page flag cells which indicate the true or non-true state of page data therein and methods of operating the same

Multi-block erase and verification circuit in a nonvolatile semiconductor memory device and a method thereof

Method and apparatus for optimizing erase and program times for a non-volatile memory device

Integrated circuit memory devices having interleaved read capability and methods of operating same

Auto-program circuit in a nonvolatile semiconductor memory device

CONVERSANT INTELLECTUAL PROPERTY MAN INC

Non-volatile memory device

Flash memory system

Non-volatile memory device having configurable page size

PYEON HONG-BEOM

Hierarchical common source line structure in NAND flash memory

OH HAKJUNE

Memory with output control