Inventor

MOHAPATRA CHANDRA S

US51 patents

⚠️ This page may combine multiple inventors who share the name “MOHAPATRA CHANDRA S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MOHAPATRA CHANDRA S

INTEL CORP

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Indium-rich NMOS transistor channels

High-mobility semiconductor source/drain spacer

Backside source/drain replacement for semiconductor devices with metallization on both sides

Pseudomorphic InGaAs on GaAs for gate-all-around transistors

Transistor with a sub-fin dielectric region under a gate

Well-based integration of heteroepitaxial N-type transistors with P-type transistors

High-electron-mobility transistors with heterojunction dopant diffusion barrier

High electron mobility transistors with localized sub-fin isolation

High mobility field effect transistors with a band-offset semiconductor source/drain spacer

Transistor fin formation via cladding on sacrificial core

High mobility field effect transistors with a retrograded semiconductor source/drain

Techniques for forming transistors on the same die with varied channel materials

Field effect transistors with gate electrode self-aligned to semiconductor fin

High-mobility semiconductor source/drain spacer

Field effect transistors with gate electrode self-aligned to semiconductor fin

FINFET transistor having a doped subfin structure to reduce channel to substrate leakage

High-mobility field effect transistors with wide bandgap fin cladding

Semiconductor device with released source and drain

Low damage self-aligned amphoteric FINFET tip doping

Transistor including tensile-strained germanium channel

Backside source/drain replacement for semiconductor devices with metallization on both sides

Geometry tuning of fin based transistor

Prevention of subchannel leakage current in a semiconductor device with a fin structure

Dopant diffusion barrier for source/drain to curb dopant atom diffusion

Indium-containing fin of a transistor device with an indium-rich core

Ingaas epi structure and wet etch process for enabling III-v GAA in art trench

Nanowire for transistor integration

Optimizing gate profile for performance and gate fill

Etching fin core to provide fin doubling

Group III-V material transistors employing nitride-based dopant diffusion barrier layer

Indium-rich NMOS transistor channels

Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers

III-V finfet transistor with V-groove S/D profile for improved access resistance

FINFET transistor having a tapered subfin structure

Apparatus and methods to create an active channel having indium rich side and bottom surfaces

Reduced leakage transistors with germanium-rich channel regions

III-V semiconductor alloys for use in the subfin of non-planar semiconductor devices and methods of forming the same

High-electron-mobility transistors with counter-doped dopant diffusion barrier

Apparatus and methods to create an indium gallium arsenide active channel having indium rich surfaces

High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin

Apparatus and methods of forming fin structures with asymmetric profile

Tensile source drain III-V transistors for mobility improved n-MOS

Crystallized silicon carbon replacement material for NMOS source/drain regions

Differential work function between gate stack metals to reduce parasitic capacitance

Beaded fin transistor

Fin-based III-V/SI or GE CMOS SAGE integration

Apparatus and methods to create a buffer to reduce leakage in microelectronic transistors

Apparatus and methods to create a buffer which extends into a gated region of a transistor

TAHOE RES LTD

FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage