Inventor

LU XUANXUAN

US36 patents

⚠️ This page may combine multiple inventors who share the name “LU XUANXUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU XUANXUAN

SK HYNIX INC

Performance of a bit flipping (BF) decoder of an error correction system

Deep learning based regression framework for read thresholds in a NAND flash memory

Error mitigation scheme for bit-flipping decoders for irregular low-density parity-check codes

Bit-flipping decoder for G-LDPC codes with syndrome-decoding for component codes

Storage device performance optimization using deep learning

Memory system and method for read operation based on grouping of word lines

Read threshold optimization systems and methods using model-less regression

Memory system for multi-clustering read thresholds and method thereof

Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes

Fast fail support for error correction in non-volatile memory

Error characteristic estimation for NAND flash

Reducing the latency of a syndrome-based quasi-cyclic decoder

Neighbor assisted correction error recovery for memory system and method thereof

Encoder for memory system and method thereof

Memory system and method for optimizing read threshold

Memory system and method for bad block management

Dynamic interleaver change for bit line failures in NAND flash storage

Decoder for memory system and method thereof

Encoder and decoder for memory system and method thereof

Memory system with soft-read suspend scheme and method of operating such memory system

Read threshold estimation systems and methods using deep learning

Descrambler for memory systems and method thereof

Read threshold optimization systems and methods by multi-dimensional search

Memory system with low-latency read recovery and method of operating the memory system

Decoder for memory system and method thereof

Hardware implementations of a quasi-cyclic syndrome decoder

Quality of service (QoS) aware data storage decoder

Soft-input soft-output component code decoder for generalized low-density parity-check codes

Decoding latency and throughput of a multi-decoder error correction system

Self-adaptive low-density parity check hard decoder

Memory system with low-complexity decoding and method of operating such memory system

Memory system with error-reduction scheme for decoding and method of operating such memory system

Read retry threshold voltage selection

Quality of service of an adaptive soft decoder

Controller with smart scheduling and method of operating the controller

MARVELL ASIA PTE LTD

Reinforcement learning-enabled low-density parity check decoder