Inventor

HSIA LIANG-CHOO

TW116 patents

⚠️ This page may combine multiple inventors who share the name “HSIA LIANG-CHOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSIA LIANG-CHOO

CHARTERED SEMICONDUCTOR MFG

Copper recess formation using chemical process for fabricating barrier cap for lines and vias

High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability

Method for forming high-K charge storage device

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

Method to fabricate Ge and Si devices together for performance enhancement

Structure and method of liner air gap formation

Use of amorphous carbon as a removable ARC material for dual damascene fabrication

Method of forming a high performance and low cost CMOS device

Entire encapsulation of Cu interconnects using self-aligned CuSiN film

Integrated circuit with protective moat

Selective oxide trimming to improve metal T-gate transistor

Formation of metal silicide layer over copper interconnect for reliability enhancement

Reliable level shifter of ultra-high voltage device used in low power application

Laser activation of implanted contact plug for memory bitline fabrication

Integrated circuit system using dual damascene process

Method to control dual damascene trench etch profile and trench depth uniformity

Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch

Polarizing photolithography system

Composite stress spacer

Combined copper plating method to improve gap fill

Protruded contact and insertion of inter-layer-dielectric material to match damascene hardmask to improve undercut for low-k interconnects

Implantation-less approach to fabricating strained semiconductor on isolation wafers

Method of forming shallow trench isolation regions with improved corner rounding

MOSEL VITELIC INC

Stacked capacitor having improved charge storage capacity

Antireflection coating for highly reflective photolithographic layers comprising chromium oxide or chromium suboxide

Circuit structure with an anti-reflective layer

Method of forming stacked capacitor having corrugated side-wall structure

Double-side corrugated cylindrical capacitor structure of high density DRAMs

Method of making corrugated cell contact

Inverse-T tungsten gate apparatus

Method of making an inverse-T tungsten gate

Method for forming metalization for inter-layer connections

Single-side corrugated cylindrical capacitor structure of high density DRAMs

IBM

CMOS transistor with two-layer inverse-T tungsten gate

Elastomeric connectors for electronic packaging and testing

Method for fabricating a MOS transistor with two-layer inverse-T tungsten gate structure

Process for fabricating a low dielectric composite substrate

Process for fabricating a low dielectric composite substrate

GLOBALFOUNDRIES SG PTE LTD

Method of manufacture an integrated circuit system with through silicon via

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

Grain boundary blocking for stress migration and electromigration improvement in CU interconnects

MOSEL VILTELIC INC

Wafer metrology pattern integrating both overlay and critical dimension features for SEM or AFM measurements

UNITED INTEGRATED CIRCUITS CORP

Method of fabricating embedded dynamic random access memory

(unassigned)

Additive metalization using photosensitive polymer as RIE mask and part of composite insulator

LIM BARBARA FONG CHIN

Defect monitoring in semiconductor device fabrication

SEAH BOON MENG

Apparatus and methods for cleaning and drying of wafers

LIU JINPING

Integrated circuit and method of fabrication thereof

LIM VICTOR SENG KEONG

Defect detection recipe definition

YELEHANKA PRADEEP RAMACHANDRAMURTHY

Integrated circuit system with through silicon via and method of manufacture thereof

LEE YONG MENG

Spacer-less low-K dielectric processes