Inverse-T tungsten gate apparatus

Abstract

A technique for fabricating an integrated circuit device 100 using an inverse-T tungsten gate structure 121 overlying a silicided layer 119 is provided. This technique uses steps of forming a high quality gate oxide layer 115 overlying a semiconductor substrate 111. The silicided layer 119 is defined overlying the gate oxide layer 115. The silicided layer 119 does not substantially react to this layer. The technique defines the inverse-T tungsten gate electrode layer 121 overlying the silicided layer 119. A top surface of this gate electrode may also be silicided 127 to further reduce the resistance of this device element.

What is claimed is: 
     
       1. A semiconductor device, said semiconductor device comprising: a semiconductor substrate having an overlying gate insulating layer;   a first silicided layer overlying said gate insulating layer wherein said first silicided layer is substantially non-reactive to said gate insulating layer; and   a gate electrode overlying said first silicided layer, said first silicided layer extending laterally from said gate electrode.   
     
     
       2. The device of claim 1 wherein said gate insulating layer is an oxide layer. 
     
     
       3. The device of claim 1 further comprising a lightly doped drain region adjacent to said gate electrode. 
     
     
       4. The device of claim 3 further comprising first sidewall spacers defined adjacent to said gate electrode. 
     
     
       5. The device of claim 4 further comprising second sidewall spacers defined adjacent to said first sidewall spacers. 
     
     
       6. The device of claim 5 further comprising a second silicided layer overlying said gate electrode and said lightly doped drain region. 
     
     
       7. The device of claim 6 further comprising source/drain regions defined adjacent to said gate electrode. 
     
     
       8. The semiconductor device of claim 1, wherein the gate electrode comprises one of a group consisting of tungsten, titanium, and polysilicon. 
     
     
       9. The semiconductor device of claim 1 wherein the first silicided layer comprises one of the group consisting of tungsten silicide, titanium silicide, platinum suicide, and cobalt silicide. 
     
     
       10. The semiconductor device of claim 7 wherein the source/drain regions are offset from said gate electrode. 
     
     
       11. The semiconductor device of claim 1 wherein the length ratio between the first silicided layer and the gate electrode is about 5:4. 
     
     
       12. The semiconductor device of claim 1 wherein the first silicided layer extends laterally from both sides of the gate electrode. 
     
     
       13. A semiconductor device, said semiconductor device comprising: a semiconductor substrate   a gate insulating layer overlying said semiconductor substrate;   a first silicided layer overlying said gate insulating layer wherein said first silicided layer is substantially non-reactive to said gate insulating layer;   a gate electrode overlying said first silicided layer, said first silicided layer extending laterally from said gate electrode;   a lightly-doped drain region in the semiconductor substrate adjacent to the gate electrode;   a sidewall spacer adjacent to the gate electrode; and   a source/drain region in the lightly-doped drain region adjacent to said sidewall spacer.   
     
     
       14. The semiconductor device of claim 13 further comprising a second silicided layer overlying the gate electrode and the source/drain region. 
     
     
       15. The semiconductor device of claim 13 wherein the gate electrode comprises one of a group consisting of tungsten, titanium, and polysilicon. 
     
     
       16. The semiconductor device of claim 13 wherein the first silicided layer comprises one of the group consisting of tungsten silicide, titanium silicide, platinum silicide, and cobalt silicide. 
     
     
       17. A semiconductor device, said semiconductor device comprising: a semiconductor substrate having an overlying gate insulating layer;   a first silicided layer overlying said gate insulating layer; and   a gate electrode overlying said first silicided layer, said first silicided layer extending laterally from said gate electrode wherein the length ratio between the first silicided layer and the gate electrode is about 5:4.