Inventor

SIRINORAKUL SARAVUTH

TH76 patents

⚠️ This page may combine multiple inventors who share the name “SIRINORAKUL SARAVUTH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIRINORAKUL SARAVUTH

SIRINORAKUL SARAVUTH

Post-mold for semiconductor package having exposed traces

Method and apparatus for no lead semiconductor package

Molded leadframe substrate semiconductor package

Method of manufacturing semiconductor package containing flip-chip arrangement

Flip chip cavity package

Singulation method for semiconductor package with plating on side of connectors

Apparatus for and methods of attaching heat slugs to package tops

Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow

Leadframe based multi terminal IC package

Package with heat transfer

Method and apparatus for no lead semiconductor package

Flip-chip leadframe semiconductor package

Post-mold for semiconductor package having exposed traces

UTAC THAI LTD

Semiconductor package including leadframe roughened with chemical etchant to prevent separation between leadframe and molding compound

Lead frame ball grid array with traces under die having interlocking features

Lead frame ball grid array with traces under die having interlocking features

Package with heat transfer

Molded leadframe substrate semiconductor package

Very extremely thin semiconductor package

Plated terminals with routing interconnections semiconductor device

Plated terminals with routing interconnections semiconductor device

Plated terminals with routing interconnections semiconductor device

Singulation method for semiconductor package with plating on side of connectors

Plated terminals with routing interconnections semiconductor device

NONDHASITTHICHAI SOMCHAI

Method for forming lead frame land grid array

Molded leadframe substrate semiconductor package

Lead frame land grid array

Very extremely thin semiconductor package

Molded leadframe substrate semiconductor package

Lead frame ball grid array with traces under die

Lead frame land grid array with routing connector trace under unit

Molded leadframe substrate semiconductor package

Molded leadframe substrate semiconductor package

Molded leadframe substrate semiconductor package

UTAC HEADQUARTERS PTE LTD

Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Semiconductor package with partial plating on contact side surfaces

Semiconductor package with plated metal shielding and a method thereof

Semiconductor package with full plating on contact side surfaces and methods thereof

Semiconductor package with partial plating on contact side surfaces

Semiconductor package with partial plating on contact side surfaces

Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Stacked dies electrically connected to a package substrate by lead terminals

Cavity wall structure for semiconductor packaging

NS ELECTRONICS BANGKOK 1993 LT

Flat no-lead semiconductor die package including stud terminals

Process of fabricating semiconductor packages using leadframes roughened with chemical etchant

Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound

Method of fabricating semiconductor chip package using screen printing of epoxy on wafer

Method of fabricating no-lead package for semiconductor die with half-etched leadframe

NONDHASITTICHAI SOMCHAI

Lead frame land grid array