Plated terminals with routing interconnections semiconductor device

Abstract

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.

What is claimed is: 
     
       1. A semiconductor package comprising:
 a. a die; 
 b. terminals, each terminal including an exposed surface that is flush with a bottom surface of the semiconductor package; 
 c. interconnection routings electrically coupling with the terminals and forming an interconnection routing layer, the interconnection routing layer coupling with the die via solder balls; and 
 d. a package compound including:
 i. a top molding compound encapsulating the interconnection routings and the die; and 
 ii. a bottom molding compound surrounding the terminals, wherein at least one of the interconnection routings includes catalytic ink on the bottom molding compound, around a perimeter of one of the terminals and extending planarly away from the one of the terminals, wherein the at least one of the interconnection routings also includes plating that is adhered to the catalytic ink and a non-exposed top surface of the one of the terminals. 
 
 
     
     
       2. The semiconductor package of  claim 1 , wherein a shape of an interconnection routing and a terminal electrically coupled with the interconnection routing is irregular to lock with the package compound. 
     
     
       3. The semiconductor package of  claim 1 , wherein a first of the interconnection routings is coupled with a second of the interconnection routings. 
     
     
       4. The semiconductor package of  claim 1 , further comprising at least one other die coupled with at least one of the die and the interconnection routing layer. 
     
     
       5. The semiconductor package of  claim 1 , further comprising solder balls coupled with the terminals, wherein the solder balls extend away from the semiconductor package. 
     
     
       6. The semiconductor package of  claim 1 , wherein a first end of the at least one of the interconnection routings is at the one of the terminals and a second end of the at least one of the interconnection routings is at a location outside an area that is beneath the die. 
     
     
       7. The semiconductor package of  claim 1 , wherein the catalytic ink is not within the perimeter of the one of the terminals. 
     
     
       8. The semiconductor package of  claim 7 , wherein a first of the interconnection routings is coupled with a second of the interconnection routings. 
     
     
       9. The semiconductor package of  claim 7 , further comprising at least one other die coupled with at least one of the die and the interconnection routing layer. 
     
     
       10. The semiconductor package of  claim 7 , further comprising solder balls coupled with the terminals, wherein the solder balls extend away from the semiconductor package. 
     
     
       11. The semiconductor package of  claim 7 , wherein a first end of the at least one of the interconnection routings is at the one of the terminals and a second end of the at least one of the interconnection routings is at a location outside an area that is beneath the die. 
     
     
       12. A semiconductor package comprising:
 a. terminals, each terminal including an exposed bottom surface; 
 b. a molding compound surrounding the terminals; 
 c. a primary routing layer positioned within the semiconductor package and including primary routings electrically coupled with the terminals, wherein at least one of the primary routings includes catalytic ink on the molding compound, around a perimeter of one of the terminals electrically coupled with the at least one of the primary routings and extending planarly the one of the terminals, wherein the at least one of the primary routings also includes plating that is adhered to the catalytic ink and a non-exposed top surface of the one of the terminals; and 
 d. at least one die electrically coupled with the primary routing layer via solder balls. 
 
     
     
       13. The semiconductor package of  claim 12 , wherein the at least one of the primary routings is electrically coupled with at least another terminal. 
     
     
       14. The semiconductor package of  claim 12 , further comprising a locking mechanism for fastening a package compound with the primary routings and the terminals. 
     
     
       15. The semiconductor package of  claim 14 , further comprising another molding compound, wherein the another molding compound encapsulates the primary routings and the at least one die. 
     
     
       16. The semiconductor package of  claim 15 , wherein the two molding compounds interface each other. 
     
     
       17. The semiconductor package of  claim 16 , wherein the package compound includes the two molding compounds. 
     
     
       18. The semiconductor package of  claim 17 , wherein the primary routings electrically coupled with the terminals extend outside an area that the at least one die is electrically coupled with the primary routing layer is located at. 
     
     
       19. The semiconductor package of  claim 12 , wherein a first end of the at least one of the interconnection routings is at the one of the terminals and a second end of the at least one of the interconnection routings is at a location outside an area that is beneath the die. 
     
     
       20. A semiconductor package comprising:
 a. a die; 
 b. terminals, each terminal including an exposed surface that is flush with a bottom surface of the semiconductor package; 
 c. interconnection routings electrically coupling with the terminals and forming an interconnection routing layer, the interconnection routing layer coupling with the die via solder balls; and 
 d. a package compound including:
 1. a top molding compound encapsulating the interconnection routings and the die; and 
 2. a bottom molding compound surrounding the terminals, wherein at least one of the interconnection routings includes catalytic ink on the bottom molding compound, around a perimeter of one of the terminals and extending planarly away from the one of the terminals, wherein the at least one of the interconnection routings also includes plating that is adhered to the catalytic ink and a non-exposed top surface of the one of the terminals, wherein a shape of an interconnection routing and a terminal electrically coupled with the interconnection routing is irregular to lock with the package compound.