Inventor

EDWARDS ANDREW P

US61 patents

⚠️ This page may combine multiple inventors who share the name “EDWARDS ANDREW P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EDWARDS ANDREW P

SEMICONDUCTOR COMPONENTS IND LLC

Method and system for fin-based voltage clamp

Negative charge extraction structure for edge termination

Method and system for etch depth control in III-V semiconductor devices

Methods and systems to improve uniformity in power FET arrays

Method and system for fabrication of a vertical fin-based field effect transistor

Self-aligned isolation for self-aligned contacts for vertical FETS

Regrowth uniformity in GaN vertical devices

Method and system for fabricating fiducials using selective area growth

Fabrication method for JFET with implant isolation

Vertical fin-based field effect transistor (FinFET) with neutralized fin tips

Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors

Vertical fin-based field effect transistor (FinFET) with connected fin tips

Coupled guard rings for edge termination

Method and system for routing of electrical conductors over neutralized power FETS

Method and system of junction termination extension in high voltage semiconductor devices

AVOGY INC

Method of fabricating a gallium nitride P-i-N diode using implantation

Method and system for junction termination in GaN materials using conductivity modulation

Monolithically integrated vertical JFET and Schottky diode

Method and system for a gallium nitride vertical transistor

Method of fabricating a GaN P-i-N diode using implantation

Edge termination by ion implantation in gallium nitride

Method and system for a GaN vertical JFET utilizing a regrown channel

Method and system for doping control in gallium nitride based devices

Method and system for a gallium nitride self-aligned vertical MESFET

Method and system for fabricating floating guard rings in GaN materials

Monolithically integrated vertical JFET and Schottky diode

Method of fabricating a gallium nitride merged P-i-N Schottky (MPS) diode

GaN vertical superjunction device structures and fabrication methods

NEXGEN POWER SYSTEMS INC

Method and system for fabricating fiducials using selective area growth

Fabrication method for JFET with implant isolation

JFET with implant isolation

Method and system for fabrication of a vertical fin-based field effect transistor

Method and system for etch depth control in III-V semiconductor devices

Regrowth uniformity in GaN vertical devices

Method and system for fabrication of a vertical fin-based field effect transistor

Method and system for fabricating fiducials using selective area growth

KIZILYALLI ISIK C

Monolithically integrated vertical JFET and Schottky diode

Method and system for a GAN vertical JFET utilizing a regrown gate

Method and system for a GaN vertical JFET utilizing a regrown channel

Method and system for doping control in gallium nitride based devices

Method of fabricating a GaN P-i-N diode using implantation

Edge termination by ion implantation in GaN

NIE HUI

Method and system for junction termination in GaN materials using conductivity modulation

GAN vertical superjunction device structures and fabrication methods

BOUR DAVID P

Method and system for formation of P-N junctions in gallium nitride based electronics

Method and system for local control of defect density in gallium nitride based electronics

DISNEY DONALD R

Method and system for fabricating floating guard rings in GaN materials

US NAVY

Silicon nitride passivation with ammonia plasma pretreatment for improving reliability of AlGaN/GaN HEMTs

ROMANO LINDA

Aluminum gallium nitride etch stop layer for gallium nitride based devices

RAJ MADHAN

GaN-based Schottky barrier diode with field plate