GAN vertical superjunction device structures and fabrication methods

Abstract

A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a III-nitride substrate of a first conductivity type; 
 a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate; 
 a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer, the first III-nitride epitaxial structure having a sidewall; 
 a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure; 
 a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial structure and a second portion of the surface of the first III-nitride epitaxial layer; 
 a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer; 
 one or more dielectric structures having at least a first surface coupled to a surface of the third III-nitride epitaxial layer; and 
 a first metal structure coupled to the third III-nitride epitaxial layer and a second surface of the one or more dielectric structures opposite the first surface. 
 
     
     
       2. The semiconductor device of  claim 1  further comprising a metal structure coupled to:
 at least one of the one or more dielectric structures; 
 the second III-nitride epitaxial structure; 
 the second III-nitride epitaxial layer; and 
 the third III-nitride epitaxial layer. 
 
     
     
       3. The semiconductor device of  claim 1  further comprising a second metal structure forming an ohmic electrical contact with the III-nitride substrate. 
     
     
       4. The semiconductor device of  claim 1  wherein the first III-nitride epitaxial structure is of the second conductivity type. 
     
     
       5. The semiconductor device of  claim 1  wherein the first III-nitride epitaxial structure has intrinsic conductivity. 
     
     
       6. The semiconductor device of  claim 1  wherein the first metal structure forms a first ohmic contact with the surface of the third III-nitride epitaxial layer further comprising:
 a second metal structure forming a second ohmic contact with the second III-nitride epitaxial structure. 
 
     
     
       7. The semiconductor device of  claim 1  wherein the second III-nitride epitaxial layer and the third III-nitride epitaxial layer are substantially charge balanced. 
     
     
       8. A vertical superjunction gate field-effect transistor structure comprising:
 a substrate comprising a III-nitride material of a first conductivity type; 
 a current blocking region coupled to the substrate and comprising a III-nitride epitaxial material; 
 a source region coupled to the current blocking region and comprising a III-nitride epitaxial material of the first conductivity type; 
 a first metal contact structure coupled to the source region; 
 a substantially charge-balanced region adjacent to the current blocking region, the substantially charge-balanced region comprising:
 a layer of III-nitride epitaxial material of the first conductivity type, and 
 a layer of III-nitride epitaxial material of a second conductivity type; 
 wherein the substantially charge-balanced region is configured to conduct a current when the transistor structure is under forward-bias conditions; 
 
 one or more dielectric structures having at least a first surface coupled to at least a portion of the substantially charge-balanced region; and 
 a second metal contact structure coupled to:
 a second surface of the one or more dielectric structures opposite the first surface, and 
 at least a portion of the substantially charge-balanced region. 
 
 
     
     
       9. The transistor structure of  claim 8  further comprising a metal-oxide-semiconductor field-effect transistor electrically coupled in series with the transistor structure.