Inventor

MA MANNY K F

US53 patents

⚠️ This page may combine multiple inventors who share the name “MA MANNY K F”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MA MANNY K F

MICRON TECHNOLOGY INC

Voltage compensating CMOS input buffer circuit

Method of making a structure for providing signal isolation and decoupling in an integrated circuit device

Laser antifuse using gate capacitor

ESD protection using selective siliciding techniques

EEPROM transistor for a DRAM

Laser antifuse using gate capacitor

Method and structure for providing signal isolation and decoupling in an integrated circuit device

Method of making EEPROM transistor for a DRAM

EEPROM transistor for a DRAM

Method for adjusting an output slew rate of a buffer

Method of making EEPROM transistor for a DRAM

Multiple staged power up of integrated circuit

Charge pump circuits and devices containing such

Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit

Input/output electrostatic discharge protection for devices with multiple individual power groups

Metal-oxide-semiconductor capacitor

System for generating configuration output signal responsive to configuration input signal, enabling configuration, and providing status signal identifying enabled configuration responsive to the output signal

Well resistor for ESD protection of CMOS circuits

Structure for ESD protection in semiconductor chips

ESD protection using selective siliciding techniques

Input/output electrostatic discharge protection for devices with multiple individual power groups

Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit

Well resistor for ESD protection of CMOS circuits

Cascode I/O driver with improved ESD operation

Cascode I/O driver with improved ESD operation

High resistance integrated circuit resistor

Field-effect transistor for one-time programmable nonvolatile memory element

Memory device with regulated power supply control

Well resistor for ESD protection of CMOS circuits

Method of fabricating a high resistance integrated circuit resistor

Matrix addressable display with electrostatic discharge protection

Cascode I/O driver with improved ESD operation

Buffer with adjustable slew rate and a method of providing an adjustable slew rate

Buffer with adjustable slew rate and a method of providing an adjustable slew rate

Memory device with regulated power supply control

Voltage generator methods and apparatus

Memory device with regulated power supply control

Multiple staged power up of integrated circuit

Super-voltage circuit with a fast reset

Voltage compensating CMOS input buffer circuit

Matrix addressable display with electrostatic discharge protection

Method and apparatus for coupling a semiconductor die to die terminals

Method and apparatus for coupling a semiconductor die to die terminals

Structure for ESD protection in semiconductor chips

Voltage compensating CMOS input buffer circuit

Super-voltage circuit with a fast reset

High resistivity integrated circuit resistor

Staggered contact placement on CMOS chip

Matrix addressable display with electrostatic discharge protection

MICRON TECHNOLOGIES INC

Method for multiple staged power up of integrated circuit