Method of making EEPROM transistor for a DRAM

Abstract

A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.

What is claimed is:  
     
       1. A method of fabricating an integrated circuit having both a dynamic random access memory (DRAM) cell and an electrically reprogrammable transistor, the method comprising the steps of: 
       forming active regions on a semiconductor substrate;  
       forming field-effect transistor (FET) source/drain regions in the active regions;  
       forming FET gate regions in the active regions and extending at least partially outside the active region;  
       forming a first insulating layer on the semiconductor substrate;  
       forming a buried contact opening through the first insulating layer and over at least a portion of an electrically programmable transistor gate region outside the active region, thereby exposing at least a portion of the underlying gate region;  
       forming a buried contact opening simultaneously with the forming of the forming of the buried contact layer over the electrically programmable transistor gate region through the first insulating layer and over at least a portion of the source drain region in the DRAM cell, thereby exposing at least a portion of the underlying source/drain region;  
       forming a conductive bottom plate layer within the buried contact openings and on the first insulating layer, thereby physically and electrically contacting the exposed portion of the underlying electrically reprogrammable transistor gate region and the DRAM cell source/drain region;  
       forming a dielectric layer on the conductive bottom plate layer and over the entire substrate to form an interpoly dielectric layer in the electrically reprogrammable transistor while simultaneously form a memory cell dielectric in the DRAM cell; and  
       forming a conductive top plate layer on the dielectric layer to form a control gate electrode in the electrically reprogrammable transistor, and simultaneously form a memory cell capacitor top plate electrode in the DRAM cell.  
     
     
       2. The method of  claim 1  wherein the gate region, conductive bottom plate layer, and conductive top plate layer comprise conductively doped polycrystalline silicon. 
     
     
       3. The method of  claim 2 , wherein the dielectric layer comprises silicon nitride. 
     
     
       4. The method of  claim 1 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       5. The method of  claim 4 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor dielectric in the DRAM cell. 
     
     
       6. The method of  claim 5 , wherein the step of forming a conductive top plate layer includes forming a control gate electrode in the electrically reprogrammable transistor, an simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       7. The method of  claim 6 , wherein the gate region, conductive bottom plate layer, and conductive top plate layer comprise conductively doped polycrystalline silicon. 
     
     
       8. A process for fabricating on a substrate an integrated circuit having both a dynamic random access memory cell and an electrically reprogrammable transistor comprising: 
       forming a plurality of active regions on the substrate and electrically isolated from each other;  
       forming a plurality of field-effect transistor (FET) source/drain regions in the active regions;  
       forming a plurality of FET gate regions in the active regions, each of the FET gate regions extending at least partially outside of the active regions;  
       forming a first insulating layer over the substrate and the active regions;  
       forming a buried contact opening through the first insulating layer and over at least a portion of an electronically programmable transistor gate region outside the active region for providing access to at least a portion of the underlying gate region;  
       forming a further buried contact opening through the first insulating layer and over at least a portion of the source/drain region in the DRAM cell for providing access to at least a portion of the underlying source/drain region;  
       forming a conductive layer within the buried contact openings and on the first insulating layer for physically and electrically contacting the exposed portion of the underlying electrically reprogrammable transistor gate region and the DRAM cell source/drain region;  
       forming a dielectric layer on the conductive bottom plate layer and over the entire substrate; and  
       forming a conductive top plate layer on the dielectric layer and patterning and etching it to electrically isolate the portions of the plate layer over each of the active areas from each other.  
     
     
       9. The method of  claim 8 , wherein the gate region, conductive layer and conductive top layer comprise conductively doped polycrystalline silicon. 
     
     
       10. The method of  claim 9 , wherein the dielectric layer comprises silicon nitride. 
     
     
       11. The method of  claim 8 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       12. The method of  claim 11 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor dielectric in the DRAM cell. 
     
     
       13. The method of  claim 12 , wherein the step of forming a conductive top plate layer includes forming a control gate electrode in the electrically reprogrammable transistor, an simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       14. The method of  claim 13 , wherein the gate region, conductive bottom plate layer, and conductive top plate layer comprise conductively doped polycrystalline silicon. 
     
     
       15. A method of fabricating a transistor floating gate, comprising: 
       forming a gate oxide layer;  
       forming a first conductive layer overlying the gate oxide layer, the first conductive layer functioning as a gate electrode of a first transistor; and  
       simultaneously forming a second conductive layer functioning as a memory cell bottom plate electrode overlying the first conductive layer and a third conductive layer, wherein the second and third conductive layers are formed over first and second buried contact openings that expose the first conductive layer and a source/drain region of a second transistor respectively and the second and third conductive layers are of an identical material and electrically isolated from each other and wherein the first buried contact opening is formed extending at least partially outside of a source/drain region controlled by the first transistor floating gate.  
     
     
       16. The method of  claim 15 , wherein the first and second conductive layers comprise conductively doped polycrystalline silicon. 
     
     
       17. A method of fabricating an integrated circuit having both a dynamic random access memory (DRAM) cell and an electrically reprogrammable transistor, the method comprising the steps of: 
       forming active regions on a semiconductor substrate;  
       forming field-effect transistor (FET) source/drain regions in the active regions;  
       forming FET gate regions in the active regions and extending at least partially outside the active region;  
       forming a first insulating layer on the semiconductor substrate;  
       forming a buried contact opening through the first insulating layer and over at least a portion of an electrically programmable transistor gate region outside the active region, thereby exposing at least a portion of the underlying gate region;  
       forming a further buried contact opening through the first insulating layer simultaneously with the forming of the forming of the first insulating layer over the electrically programmable transistor gate region and over at least a portion of the source drain region in the DRAM cell, thereby exposing at least a portion of the underlying source/drain region;  
       forming a conductive bottom plate layer within the buried contact openings and on the first insulating layer, thereby physically and electrically contacting the exposed portion of the underlying electrically reprogrammable transistor gate region and the DRAM cell source/drain region;  
       forming a dielectric layer on the conductive bottom plate layer and over the entire substrate to form an interpoly dielectric layer in the electrically reprogrammable transistor while simultaneously forming a memory cell dielectric in the DRAM cell; and  
       forming a conductive top plate layer on the dielectric layer to form a control gate electrode in the electrically reprogrammable transistor, and simultaneously form a memory cell capacitor top plate electrode in the DRAM cell.  
     
     
       18. The method of  claim 17 ,wherein the gate region, conductive bottom plate layer, and conductive top plate layer comprise conductively doped polycrystalline silicon. 
     
     
       19. The method of  claim 17 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       20. The method of  claim 19 , wherein the step of forming a dielectric layer includes forming an interpoly dielectric layer in the electrically reprogrammable transistor, and simultaneously forming a memory cell capacitor dielectric in the DRAM cell. 
     
     
       21. The method of  claim 20 , wherein the step of forming a conductive top plate layer includes forming a control gate electrode in the electrically reprogrammable transistor, an simultaneously forming a memory cell capacitor top plate electrode in the DRAM cell. 
     
     
       22. The method of  claim 21 , wherein the gate region, conductive bottom plate layer, and conductive top plate layer comprise conductively doped polycrystalline silicon.