Inventor
MA WILLIAM HSIOH-LIEN
US25 patents
⚠️ This page may combine multiple inventors who share the name “MA WILLIAM HSIOH-LIEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
24 patentsUS6915333B2Jul 5, 2005
Method of managing attached document
IBM82 citations97
US6506660B2Jan 14, 2003
Semiconductor with nanoscale features
IBM101 citations97
US6184151B1Feb 6, 2001
Method for forming cornered images on a substrate and photomask formed thereby
IBM92 citations97
US6358813B1Mar 19, 2002
Method for increasing the capacitance of a semiconductor capacitors
IBM56 citations96
US5923090AJul 13, 1999
Microelectronic package and fabrication thereof
IBM68 citations96
US5831301ANov 3, 1998
Trench storage dram cell including a step transfer device
IBM80 citations96
US5959325ASep 28, 1999
Method for forming cornered images on a substrate and photomask formed thereby
IBM43 citations95
US6788316B1Sep 7, 2004
Method of designating multiple hypertext links to be sequentially viewed
IBM60 citations94
US6291858B1Sep 18, 2001
Multistack 3-dimensional high density semiconductor device and method for fabrication
IBM74 citations94
US6063658AMay 16, 2000
Methods of making a trench storage DRAM cell including a step transfer device
IBM31 citations93
US7548952B2Jun 16, 2009
Method of sending an email to a plurality of recipients with selective treatment of attached files
IBM30 citations92
US6025242AFeb 15, 2000
Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
IBM22 citations92
US5998248ADec 7, 1999
Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
IBM19 citations92
US5998273ADec 7, 1999
Fabrication of semiconductor device having shallow junctions
IBM25 citations92
US4187331AFeb 5, 1980
Fluorine plasma resist image hardening
IBM23 citations82
US4013485AMar 22, 1977
Process for eliminating undesirable charge centers in MIS devices
IBM24 citations81
US6281576B1Aug 28, 2001
Method of fabricating structure for chip micro-joining
IBM11 citations74
US6232170B1May 15, 2001
Method of fabricating trench for SOI merged logic DRAM
IBM13 citations74
US6066526AMay 23, 2000
Method of making trench DRAM
IBM9 citations74
US6342323B1Jan 29, 2002
Alignment methodology for lithography
IBM12 citations73
US6022771AFeb 8, 2000
Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
IBM14 citations73
US6451634B2Sep 17, 2002
Method of fabricating a multistack 3-dimensional high density semiconductor device
IBM8 citations72
US6548345B2Apr 15, 2003
Method of fabricating trench for SOI merged logic DRAM
IBM5 citations63
US7790527B2Sep 7, 2010
High-voltage silicon-on-insulator transistors and methods of manufacturing the same
IBM0 citations52