Method of fabricating a multistack 3-dimensional high density semiconductor device

Abstract

A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

What is claimed is:  
     
       1. A method for fabricating a multistack 3-D semiconductor structure comprising: 
       providing a first level structure comprising a semiconductor substrate and a first active device;  
       providing an insulating layer on the first level structure and electrical interconnections to connect selected portions of the first level structure to subsequently to be provided second level structure;  
       adhering a second semiconductor substrate on top of the insulating layer and thinning the second semiconductor substrate and thereafter forming second active devices in the second semiconductor substrate; and wherein the first active devices are more heat tolerant in device design than the second active devices; and  
       making electrical interconnections between the first level structure and second active devices.  
     
     
       2. The method of  claim 1  wherein the first semiconductor substrate is a SOI structure. 
     
     
       3. The method of  claim 1  wherein the first semiconductor substrate comprises monocrystalline silicon. 
     
     
       4. The method of  claim 1  wherein the first active device comprise at least one member selected from the group consisting of resistor, capacitor, diode and transistor. 
     
     
       5. The method of  claim 1  wherein the electrical interconnections comprise doped polycrystalline silicon. 
     
     
       6. The method of  claim 1  which comprises reducing the thickness of the second semiconductor substrate by ion implanting into the second semiconductor substrate ions selected from the group consisting of hydrogen, rare gas ions and mixtures thereof, then bonding the second semiconductor substrate to the insulating layer and then subjecting the substrate to thermal treatment at a temperature above that for the ion implanting thereby causing separation of a thin substrate layer bonded to the insulating layer from the remainder of the second semiconductor substrate. 
     
     
       7. The method of  claim 1  wherein the thickness of the second semiconductor substrate is about 500 to about 2500 Å. 
     
     
       8. The method of  claim 1  wherein the insulating layer comprises silicon dioxide. 
     
     
       9. The method of  claim 1  which further comprises providing local electrical interconnection between the first active device and at least one other active device of the first level structure. 
     
     
       10. The method of  claim 9  wherein the local electrical interconnection comprises doped polycrystalline silicon. 
     
     
       11. The method of  claim 1  which further comprises providing an insulating layer above the second level structure. 
     
     
       12. A multistack 3-D semiconductor structure obtained by the method of  claim 1 .