Inventor
KUMAR SUDARSHAN
US32 patents
⚠️ This page may combine multiple inventors who share the name “KUMAR SUDARSHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS6707318B2Mar 16, 2004
Low power entry latch to interface static logic with dynamic logic
INTEL CORP22 citations92
US6351151B2Feb 26, 2002
Method and apparatus for reducing soft errors in dynamic circuits
INTEL CORP16 citations92
US5661675AAug 26, 1997
Positive feedback circuit for fast domino logic
INTEL CORP43 citations89
US6952118B2Oct 4, 2005
Gate-clocked domino circuits with reduced leakage current
INTEL CORP17 citations83
US6820106B1Nov 16, 2004
Method and apparatus for improving the performance of a floating point multiplier accumulator
INTEL CORP15 citations82
US6631093B2Oct 7, 2003
Low power precharge scheme for memory bit lines
INTEL CORP16 citations81
US5581497ADec 3, 1996
Carry skip adder with enhanced grouping scheme
INTEL CORP16 citations74
US5136539AAug 4, 1992
Adder with intermediate carry circuit
INTEL CORP14 citations74
US4905180AFeb 27, 1990
MOS adder with minimum pass gates in carry line
INTEL CORP19 citations74
US6292029B1Sep 18, 2001
Method and apparatus for reducing soft errors in dynamic circuits
INTEL CORP11 citations73
US5579254ANov 26, 1996
Fast static CMOS adder
INTEL CORP13 citations73
US5471414ANov 28, 1995
Fast static CMOS adder
INTEL CORP11 citations73
US6124737ASep 26, 2000
Low power clock buffer having a reduced, clocked, pull-down transistor
INTEL CORP9 citations72
US6058403AMay 2, 2000
Broken stack priority encoder
INTEL CORP10 citations71
US6629194B2Sep 30, 2003
Method and apparatus for low power memory bit line precharge
INTEL CORP11 citations70
US5900744AMay 4, 1999
Method and apparatus for providing a high speed tristate buffer
INTEL CORP7 citations69
US6833735B2Dec 21, 2004
Single stage pulsed domino circuit for driving cascaded skewed static logic circuits
INTEL CORP11 citations68
US6266757B1Jul 24, 2001
High speed four-to-two carry save adder
INTEL CORP5 citations63
US5944777AAug 31, 1999
Method and apparatus for generating carries in an adder circuit
INTEL CORP4 citations63
US6593776B2Jul 15, 2003
Method and apparatus for low power domino decoding
INTEL CORP3 citations62
US5889693AMar 30, 1999
CMOS sum select incrementor
INTEL CORP6 citations62
US6205463B1Mar 20, 2001
Fast 2-input 32-bit domino adder
INTEL CORP6 citations60
US6127850AOct 3, 2000
Low power clock buffer with shared, clocked transistor
INTEL CORP5 citations60
US6111435AAug 29, 2000
Low power multiplexer with shared, clocked transistor
INTEL CORP2 citations60
US6023767AFeb 8, 2000
Method for verifying hold time in integrated circuit design
INTEL CORP5 citations55
US5608741AMar 4, 1997
Fast parity generator using complement pass-transistor logic
INTEL CORP4 citations51
US7685451B2Mar 23, 2010
Method and apparatus to limit current-change induced voltage changes in a microcircuit
INTEL CORP1 citations49
US6628539B2Sep 30, 2003
Multi-entry register cell
INTEL CORP0 citations49
US6369616B1Apr 9, 2002
Low power clock buffer with shared, precharge transistor
INTEL CORP1 citations49
US6341099B1Jan 22, 2002
Reducing power consumption in a data storage device
INTEL CORP0 citations49