Low power entry latch to interface static logic with dynamic logic

Abstract

An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

What is claimed is:  
     
       1. A latch comprising: 
       a ground rail;  
       a power rail;  
       a node;  
       an output port;  
       an inverter coupled to the node to provide at the output port a HIGH voltage if the node is LOW and a LOW voltage if the node is HIGH;  
       a first pullup transistor to provide a low impedance path between the node and the power rail during a precharge phase;  
       a pulldown network to conditionally provide a low impedance path between the node and the ground rail for a portion of time during an evaluation phase;  
       a second pullup transistor to provide a low impedance path between the node and the power rail only if ON; and  
       a pass transistor coupling the output port to the second pullup transistor to switch the second pullup transistor ON only during an evaluation phase and only if the output port voltage is LOW.  
     
     
       2. The latch as set forth in  claim 1 , further comprising: 
       a third pullup transistor coupled to the logic gate to switch the second pullup transistor OFF during a precharge phase.  
     
     
       3. The latch as set forth in  claim 2 , 
       wherein the inverter has an input port connected to the node and an output port connected to the latch output port;  
       wherein the pass transistor has a first source/drain connected to the output node and a second source/drain; and  
       wherein the second pullup transistor is a pMOSFET having a gate connected to the second source/drain of the nMOSFET and a drain connected to the node.  
     
     
       4. A latch comprising: 
       a node;  
       an output port;  
       a ground rail;  
       a clock port;  
       a pulldown network to conditionally provide a low impedance path between the node and the ground rail during a portion of time for which the clock port is held HIGH;  
       a first pullup pMOSFET having a gate connected to the clock port, and a drain connected to the node;  
       an inverter having an input port connected to the node and an output port connected to the output port;  
       a pass transistor having a gate coupled to the clock port, a first source/drain connected to the output node, and a second source/drain;  
       a second pullup pMOSFET having a gate connected to the second source/drain of the pass transistor, and having a drain connected to the node; and  
       a third pullup pMOSFET having a gate connected to the clock port, and a drain connected to the gate of the second pullup pMOSFET.  
     
     
       5. The latch as set forth in  claim 4 , further comprising: 
       a power rail;  
       wherein the first, second, and third pullup pMOSFETs have sources connected to the power rail.  
     
     
       6. The latch as set forth in  claim 5 , wherein the pass transistor is a nMOSFET having a gate connected to the clock port. 
     
     
       7. The latch as set forth in  claim 4 , wherein the pass transistor is a nMOSFET having a gate connected to the clock port. 
     
     
       8. A latch to provide a dynamic signal at an output port in response to at least one static signal at a least one input port, the latch comprising: 
       a node;  
       a clock port;  
       a first pullup pMOSFET having a gate connected to the clock port, and a drain connected to the node;  
       a first nMOSFET having a gate connected to the clock port, a drain connected to the node, and a source;  
       a pulldown network coupled to the at least one input port and to the first nMOSFET;  
       a second nMOSFET having a drain connected to the pulldown network, and a gate;  
       a first inverter having an input port connected to the clock port and an output port connected to the gate of the second nMOSFET;  
       a second inverter having an input port connected to the node, and an output port connected to the output port of the latch;  
       a second pullup pMOSFET having a drain connected to the node, and a gate; and  
       a pass transistor having a first source/drain connected to the output port, a second source/drain connected to the gate of the second pullup pMOSFET, and a gate coupled to the clock port.  
     
     
       9. The latch as set forth in  claim 8 , wherein the pass transistor is a nMOSFET having its gate connected to the clock port. 
     
     
       10. The latch as set forth in  claim 9 , further comprising: 
       a third pullup pMOSFET having a drain connected to the gate of the second pullup pMOSFET and a gate connected to the gate of the pass transistor.  
     
     
       11. The latch as set forth in  claim 8 , further comprising: 
       a third pullup pMOSFET having a drain connected to the gate of the second pullup pMOSFET and a gate coupled to the gate of the pass transistor.  
     
     
       12. A computer system comprising: 
       a microprocessor; and  
       a volatile memory connected to the microprocessor;  
       wherein the microprocessor comprises:  
       a ground rail;  
       a power rail;  
       a node;  
       an output port;  
       an inverter coupled to the node to provide at the output port a HIGH voltage if the node is LOW and a LOW voltage if the node is HIGH;  
       first pullup transistor to provide a low impedance path between the node and the power rail during a precharge phase;  
       a pulldown network to conditionally provide a low impedance path between the node and the ground rail for a portion of time during an evaluation phase;  
       a second pullup transistor to provide a low impedance path between the node and the power rail only if ON; and  
       a pass transistor coupling the output port to the second pullup transistor to switch the second pullup transistor ON only during an evaluation phase and only if the output port voltage is LOW.  
     
     
       13. An entry latch to provide a dynamic signal in response to at least one input static signal, the entry latch comprising: 
       a node;  
       an output port to provide the dynamic signal;  
       a pulidown network having at least one input port to receive the at least one input static signal, the pulldown network to conditionally discharge the node depending upon the at least one input static signal;  
       a first pullup pMOSFET having a gate, and a drain connected to the node; and  
       a pass transistor having a gate, a first source/drain connected to the output port, and a second source/drain connected to a gate of the first pullup pMOSFET, wherein the first pullup pMOSFET turns ON only during an evaluation phase and only if the pulldown network does not turn ON.  
     
     
       14. The entry latch as set forth in  claim 13 , further comprising: 
       a second pullup pMOSFET having a drain connected to the gate of the first pullup pMOSFET, and a gate coupled to the gate of the pass transistor.  
     
     
       15. The entry latch as set forth in  claim 14 , wherein the pass transistor is a nMOSFET and the gate of the second pullup pMOSFET is connected to the gate of the pass nMOSFET.