Inventor

TRIVEDI JIGISH D

US97 patents

⚠️ This page may combine multiple inventors who share the name “TRIVEDI JIGISH D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRIVEDI JIGISH D

MICRON TECHNOLOGY INC

Capacitorless DRAM on bulk silicon

Methods of forming recessed access devices associated with semiconductor constructions

Local interconnect structures and methods for making the same

Local interconnect comprising titanium nitride barrier layer

Method for forming a notched damascene planar poly/metal gate

Methods for forming shallow trench isolation

Sub-micron space liner and densification process

Method of forming a field effect transistor

Semiconductor processing methods, and semiconductor constructions

Methods of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry

Integrated circuitry and semiconductor processing method of forming field effect transistors

Method of forming a local interconnect including selectively etched conductive layers and recess formation

Dual depth trench isolation

Suppression of cross diffusion and gate depletion

Edge intensive antifuse device structure

Transistor gate and local interconnect

Process for forming low resistance metal silicide local interconnects

Cross-diffusion resistant dual-polycide semiconductor structure and method

Stacked local interconnect structure and method of fabricating same

Stacked local interconnect structure and method of fabricating same

Methods of forming integrated circuitry

Method of forming plugs and local interconnect for embedded memory/system-on-chip (SOC) applications

Methods of forming transistors

Method of forming an integrated circuitry isolation trench, method of forming integrated circuitry, and integrated circuitry

Low resistance metal silicide local interconnects and a method of making

Methods of forming recessed access devices associated with semiconductor constructions

Liner for shallow trench isolation

Method of forming a dual damascene interconnect by selective metal deposition

MOS transistors with nitrogen in the gate oxide of the p-channel transistor

Semiconductor processing method of forming field effect transistors

Dual damascene interconnect

P-type FET in a CMOS with nitrogen atoms in the gate dielectric

Liner for shallow trench isolation

Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same

Method for forming a notched gate

Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications

Recessed access device for a memory

Method for forming an antifuse

Method of forming a field effect transistor with halo implant regions

Method of forming a field effect transistor

Edge intensive antifuse

Integrated transistor circuitry

Local interconnect structure for integrated circuit devices, source structure for the same, and method for fabricating the same

Method to fabricate surface p-channel CMOS

Dual depth trench isolation

Sidewall strap for complementary semiconductor structures and method of making same

Method for forming an antifuse

Dual damascene interconnect

Conductive structure in an integrated circuit

PAREKH KUNAL R

Methods of forming recessed access devices associated with semiconductor constructions