Inventor

MEHANDRU RISHABH

US137 patents

Patents

50 patents

US10886217B2Jan 5, 2021

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

INTEL CORP20 citations94

US10872820B2Dec 22, 2020

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

INTEL CORP11 citations84

US11094716B2Aug 17, 2021

Source contact and channel interface to reduce body charging from band-to-band tunneling

INTEL CORP6 citations83

US11527612B2Dec 13, 2022

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

INTEL CORP6 citations74

US11367722B2Jun 21, 2022

Stacked nanowire transistor structure with different channel geometries for stress

INTEL CORP6 citations74

US12107085B2Oct 1, 2024

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

INTEL CORP2 citations73

US11869890B2Jan 9, 2024

Stacked transistors with contact last

INTEL CORP2 citations73

US11824107B2Nov 21, 2023

Wrap-around contact structures for semiconductor nanowires and nanoribbons

INTEL CORP2 citations73

US11742346B2Aug 29, 2023

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

INTEL CORP3 citations73

US11664377B2May 30, 2023

Forksheet transistor architectures

INTEL CORP2 citations73

US11658221B2May 23, 2023

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP3 citations73

US11640961B2May 2, 2023

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

INTEL CORP2 citations73

US11616015B2Mar 28, 2023

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

INTEL CORP3 citations73

US11573798B2Feb 7, 2023

Stacked transistors with different gate lengths in different device strata

INTEL CORP1 citations73

US11527640B2Dec 13, 2022

Wrap-around contact structures for semiconductor nanowires and nanoribbons

INTEL CORP3 citations73

US11462536B2Oct 4, 2022

Integrated circuit structures having asymmetric source and drain structures

INTEL CORP5 citations73

US11430868B2Aug 30, 2022

Buried etch-stop layer to help control transistor source/drain depth

INTEL CORP2 citations73

US11411119B2Aug 9, 2022

Double gated thin film transistors

INTEL CORP3 citations73

US11393818B2Jul 19, 2022

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

INTEL CORP2 citations73

US11387238B2Jul 12, 2022

Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

INTEL CORP2 citations73

US11373999B2Jun 28, 2022

Deep trench via for three-dimensional integrated circuit

INTEL CORP3 citations73

US11362189B2Jun 14, 2022

Stacked self-aligned transistors with single workfunction metal

INTEL CORP4 citations73

US11282861B2Mar 22, 2022

Dynamic logic built with stacked transistors sharing a common gate

INTEL CORP5 citations73

US11276780B2Mar 15, 2022

Transistor contact area enhancement

INTEL CORP2 citations73

US11264500B2Mar 1, 2022

Device isolation

INTEL CORP4 citations73

US11075198B2Jul 27, 2021

Stacked transistor architecture having diverse fin geometry

INTEL CORP3 citations73

US10896963B2Jan 19, 2021

Semiconductor device contacts with increased contact area

INTEL CORP2 citations73

US10784358B2Sep 22, 2020

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP3 citations73

US10600810B2Mar 24, 2020

Backside fin recess control with multi-hsi option

INTEL CORP2 citations73

US10546873B2Jan 28, 2020

Integrated circuit with stacked transistor devices

INTEL CORP5 citations73

US10453967B2Oct 22, 2019

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

INTEL CORP3 citations73

US10411090B2Sep 10, 2019

Hybrid trigate and nanowire CMOS device architecture

INTEL CORP6 citations73

US11404319B2Aug 2, 2022

Vertically stacked finFETs and shared gate patterning

INTEL CORP5 citations72

US11342432B2May 24, 2022

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

INTEL CORP1 citations72

US12349420B2Jul 1, 2025

Device, method and system to provide a stressed channel of a transistor

INTEL CORP0 citations63

US12288810B2Apr 29, 2025

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP0 citations63

US12057494B2Aug 6, 2024

Stacked transistors

INTEL CORP0 citations63

US11942526B2Mar 26, 2024

Integrated circuit contact structures

INTEL CORP0 citations63

US11935891B2Mar 19, 2024

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

INTEL CORP0 citations63

US11935933B2Mar 19, 2024

Backside contact structures and fabrication for metal on both sides of devices

INTEL CORP0 citations63

US11894262B2Feb 6, 2024

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

INTEL CORP0 citations63

US11721735B2Aug 8, 2023

Thin film transistors having U-shaped features

INTEL CORP0 citations63

US11705518B2Jul 18, 2023

Isolation schemes for gate-all-around transistor devices

INTEL CORP0 citations63

US11688637B2Jun 27, 2023

Wrap-around contact structures for semiconductor fins

INTEL CORP0 citations63

Showing the top 50 of 137 patents by PatentIndex Score.

MEHANDRU RISHABH

Patents

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Integrated circuit structures

Thin film transistors having U-shaped features

Forksheet transistor architectures

Backside contact structures and fabrication for metal on both sides of devices

Integrated circuit device with crenellated metal trace layout

Stacked channel structures for MOSFETs

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Source contact and channel interface to reduce body charging from band-to-band tunneling

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

Stacked nanowire transistor structure with different channel geometries for stress

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors with contact last

Wrap-around contact structures for semiconductor nanowires and nanoribbons

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Forksheet transistor architectures

Backside contact structures and fabrication for metal on both sides of devices

III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Stacked transistors with different gate lengths in different device strata

Wrap-around contact structures for semiconductor nanowires and nanoribbons

Integrated circuit structures having asymmetric source and drain structures

Buried etch-stop layer to help control transistor source/drain depth

Double gated thin film transistors

Stacked transistors with Si PMOS and high mobility thin film transistor NMOS

Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices

Deep trench via for three-dimensional integrated circuit

Stacked self-aligned transistors with single workfunction metal

Dynamic logic built with stacked transistors sharing a common gate

Transistor contact area enhancement

Device isolation

Stacked transistor architecture having diverse fin geometry

Semiconductor device contacts with increased contact area

Backside contact structures and fabrication for metal on both sides of devices

Backside fin recess control with multi-hsi option

Integrated circuit with stacked transistor devices

Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device

Hybrid trigate and nanowire CMOS device architecture

Vertically stacked finFETs and shared gate patterning

Gate-all-around integrated circuit structures having insulator fin on insulator substrate

Device, method and system to provide a stressed channel of a transistor

Backside contact structures and fabrication for metal on both sides of devices

Stacked transistors

Integrated circuit contact structures

Non-silicon N-type and P-type stacked transistors for integrated circuit devices

Backside contact structures and fabrication for metal on both sides of devices

Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures

Thin film transistors having U-shaped features

Isolation schemes for gate-all-around transistor devices

Wrap-around contact structures for semiconductor fins