Inventor · disambiguated record
Michael L. Bushnell
Also filed as: BUSHNELL MICHAEL · BUSHNELL MICHAEL L
8 granted patents·1 pending application·171 citations·filing 1993–2023
88Inventor score
Top patents by PatentIndex Score
9 records- 0178US6247154B1Method and apparatus for combined stuck-at fault and partial-scanned delay-fault built-in self testUNIV RUTGERS·Filed 1999·Granted Jun 12, 2001·52 cites·25 claims
- 0269US8164345B2Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testabilityBUSHNELL MICHAEL L·Filed 2009·Granted Apr 24, 2012·9 cites·8 claims
- 0369US7810053B2Method and system of dynamic power cutoff for active leakage reduction in circuitsBUSHNELL MICHAEL·Filed 2007·Granted Oct 5, 2010·11 cites·22 claims
- 0463US6308300B1Test generation for analog circuits using partitioning and inverted system simulationUNIV RUTGERS·Filed 1999·Granted Oct 23, 2001·27 cites·21 claims
- 0562US6812724B2Method and system for graphical evaluation of IDDQ measurementsFiled 2003·Granted Nov 2, 2004·15 cites·44 claims
- 0656US5422891ARobust delay fault built-in self-testing method and apparatusUNIV RUTGERS·Filed 1993·Granted Jun 6, 1995·35 cites·19 claims
- 0749US2024126968A1Automatic blocking of unknown signals and grading of test point sites using untestable fault estimates to improve ic testabilityBUSHNELL MICHAEL L·Filed 2023·Application pending·0 cites
- 0842US6131181AMethod and system for identifying tested path delay faultsUNIV RUTGERS·Filed 1997·Granted Oct 10, 2000·13 cites·24 claims
- 0937US5831437ATest generation using signal flow graphsUNIV RUTGERS·Filed 1996·Granted Nov 3, 1998·9 cites·13 claims
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