Inventor
KOBRINSKY MAURO
US27 patents
Patents
27 patentsUS9391019B2Jul 12, 2016
Scalable interconnect structures with selective via posts
INTEL CORP26 citations92
US10685949B2Jun 16, 2020
Flexible electronic system with wire bonds
INTEL CORP4 citations73
US11830788B2Nov 28, 2023
Integrated circuits and methods for forming integrated circuits
INTEL CORP2 citations72
US11410928B2Aug 9, 2022
Device layer interconnects
INTEL CORP1 citations72
US11189585B2Nov 30, 2021
Selective recess of interconnects for probing hybrid bond devices
INTEL CORP3 citations72
US11171239B2Nov 9, 2021
Transistor channel passivation with 2D crystalline material
INTEL CORP2 citations72
US9591758B2Mar 7, 2017
Flexible electronic system with wire bonds
INTEL CORP4 citations70
US10204855B2Feb 12, 2019
Bendable and stretchable electronic devices and methods
INTEL CORP3 citations69
US11721554B2Aug 8, 2023
Stress compensation for wafer to wafer bonding
INTEL CORP2 citations68
US12211794B2Jan 28, 2025
Integrated circuits and methods for forming thin film crystal layers
INTEL CORP0 citations62
US12107170B2Oct 1, 2024
Transistor channel passivation with 2D crystalline material
INTEL CORP0 citations62
US11276644B2Mar 15, 2022
Integrated circuits and methods for forming thin film crystal layers
INTEL CORP1 citations62
US11164809B2Nov 2, 2021
Integrated circuits and methods for forming integrated circuits
INTEL CORP0 citations62
US12506059B2Dec 23, 2025
Vertically spaced intra-level interconnect line metallization for integrated circuit devices
INTEL CORP0 citations61
US12342574B2Jun 24, 2025
Contact resistance reduction in transistor devices with metallization on both sides
INTEL CORP0 citations61
US12315794B2May 27, 2025
Skip level vias in metallization layers for integrated circuit devices
INTEL CORP0 citations61
US12288746B2Apr 29, 2025
Skip level vias in metallization layers for integrated circuit devices
INTEL CORP0 citations61
US11948874B2Apr 2, 2024
Vertically spaced intra-level interconnect line metallization for integrated circuit devices
INTEL CORP0 citations61
US12426342B2Sep 23, 2025
Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability
INTEL CORP0 citations59
US12394716B2Aug 19, 2025
Integrated circuit interconnect structures with graphene cap
INTEL CORP1 citations59
US12199143B2Jan 14, 2025
Gate-all-around integrated circuit structures having removed substrate
INTEL CORP0 citations52
US12513984B2Dec 30, 2025
Double-sided integrated circuit transistor structures with depopulated bottom channel regions
INTEL CORP0 citations51
US11985909B2May 14, 2024
Fabrication of stackable embedded eDRAM using a binary alloy based on antimony
INTEL CORP0 citations51
US12334392B2Jun 17, 2025
Multi-height interconnect trenches for resistance and capacitance optimization
INTEL CORP0 citations50
US12598977B2Apr 7, 2026
Fill of vias in single and dual damascene structures using self-assembled monolayer
INTEL CORP0 citations49
US11532558B2Dec 20, 2022
Metallization barrier structures for bonded integrated circuit interfaces
INTEL CORP0 citations49
US12506075B2Dec 23, 2025
Epitaxial source/drain back-side device contact structures with wrap around metallization and protective conformal liner
INTEL CORP0 citations45