Inventor

CHEN FUSEN E

US51 patents

⚠️ This page may combine multiple inventors who share the name “CHEN FUSEN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN FUSEN E

SGS THOMSON MICROELECTRONICS

Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby

Integrated circuit with planarized shallow trench isolation

Integrated circuit metallization with zero contact enclosure requirements and method of making the same

Method of forming isolated regions of oxide

Method for forming a metal contact

Method of forming vias

Integrated circuit device structure with dielectric and metal stacked plug in contact hole

Integrated circuit metallization with zero contact enclosure requirements

Interconnect and resistor for integrated circuits

Semiconductor bond pad structure and method

Method for planarized isolation for cmos devices

Field progammable device with contact openings

Semiconductor bond pad structure and method

Local interconnect process for integrated circuits

Method of forming submicron contacts

Planar contact with a void

Method of forming a planar contact with a void

Transistor spacer etch pinpoint structure

Method of forming vias for multilevel metallization

Semiconductor contact via structure and method

Planarized isolation structure for CMOS devices

Method to improve step coverage by contact reflow

Semiconductor contact via structure having amorphous silicon side walls

Interconnect and resistor for integrated circuits

Method for forming polycrystalline silicon contacts

Local interconnect process for integrated circuits

Interconnect for integrated circuits

Local interconnect for integrated circuits

Method to imporve metal step coverage by contact reflow

APPLIED MATERIALS INC

Method of preventing diffusion of copper through a tantalum-comprising barrier layer

Method of depositing a tantalum nitride/tantalum diffusion barrier layer system

Method of depositing a metal seed layer on semiconductor substrates

Damage-free sculptured coating deposition

Method of depositing a metal seed layer on semiconductor substrates

Metal / metal nitride barrier layer for semiconductor device applications

Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features

Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate

Method for depositing a diffusion barrier layer and a metal conductive layer

Method of depositing a sculptured copper seed layer

ST MICROELECTRONICS INC

Method of producing an aluminum stacked contact/via for multilayer

Method for making transistor spacer etch pinpoint structure

Method of forming a field programmable device

Method for forming a metal contact

Method of forming isolated regions of oxide

Method for forming a metal contact

Structure and method of forming vias

Method for fabricating interlevel contacts of aluminum/refractory metal alloys

Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature

CHIANG TONY

Method for depositing a diffusion barrier layer and a metal conductive layer

Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features