Inventor

WEI CHE-CHIA

US47 patents

⚠️ This page may combine multiple inventors who share the name “WEI CHE-CHIA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEI CHE-CHIA

SGS THOMSON MICROELECTRONICS

Gate overlapping LDD structure

Method of forming isolated regions of oxide

Method for forming a metal contact

Method of forming a gate overlap LDD structure

Local interconnect for integrated circuits

Semiconductor contact via structure and method

Method of forming an integrated circuit device

Self-aligned contact process

Semiconductor contact via structure and method

Local interconnect for integrated circuits

Method for fabricating an interconnect structure in an integrated circuit

Semiconductor contact via structure having amorphous silicon side walls

Interconnect structure for an integrated circuit

Method for forming interconnect in integrated circuits

Poly-buffered LOCOS process

Self-aligned contact process

Programmable contact structure

Structure and method for fabricating integrated circuits

TEXAS INSTRUMENTS INC

Process for patterning local interconnects

SRAM with local interconnect

Oxide-isolated source/drain transistor

Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects

Method of making oxide-isolated source/drain transistor

CMOS device with both p+ and n+ gates

Process for formation of shallow silicided junctions

Local interconnect

Oxide-capped titanium silicide formation

Process to increase tin thickness

Selective silicidation process using a titanium nitride protective layer

Oxide-capped titanium silicide formation

Titanium silicide local interconnect process

Silicided structures having openings therein

ST MICROELECTRONICS INC

Semiconductor contact via structure

Method for forming programmable contact structure

Having halo regions integrated circuit device structure

Method for forming a metal contact

Method of forming an integrated circuit device

Method of forming isolated regions of oxide

Method for forming a metal contact

Method for fabricating interlevel contacts of aluminum/refractory metal alloys

Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature

CHARTERED SEMICONDUCTOR MFG

Method of making back gate contact for silicon on insulator technology

Semiconductor contact metallization

Method for making electrical local interconnects

Method for forming integrated circuit device structures from semiconductor substrate oxidation mask layers

Definition of anti-fuse cell for programmable gate array application

CHARTERED SEMICONDUCTOR MFG CO

Definition of anti-fuse cell for programmable gate array application