Inventor
POPLEVINE PAVEL
US45 patents
⚠️ This page may combine multiple inventors who share the name “POPLEVINE PAVEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NAT SEMICONDUCTOR CORP
40 patentsUS6711051B1Mar 23, 2004
Static RAM architecture with bit line partitioning
NAT SEMICONDUCTOR CORP82 citations97
US6985386B1Jan 10, 2006
Programming method for nonvolatile memory cell
NAT SEMICONDUCTOR CORP30 citations93
US6525397B1Feb 25, 2003
Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology
NAT SEMICONDUCTOR CORP38 citations93
US6420217B1Jul 16, 2002
Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology
NAT SEMICONDUCTOR CORP33 citations93
US6384398B1May 7, 2002
CMOS compatible pixel cell that utilizes a gated diode to reset the cell
NAT SEMICONDUCTOR CORP17 citations93
US6380571B1Apr 30, 2002
CMOS compatible pixel cell that utilizes a gated diode to reset the cell
NAT SEMICONDUCTOR CORP16 citations93
US6122204ASep 19, 2000
Sense amplifier having a bias circuit with a reduced size
NAT SEMICONDUCTOR CORP26 citations93
US6031275AFeb 29, 2000
Antifuse with a silicide layer overlying a diffusion region
NAT SEMICONDUCTOR CORP25 citations93
US7239558B1Jul 3, 2007
Method of hot electron injection programming of a non-volatile memory (NVM) cell array in a single cycle
NAT SEMICONDUCTOR CORP28 citations92
US7167392B1Jan 23, 2007
Non-volatile memory cell with improved programming technique
NAT SEMICONDUCTOR CORP35 citations92
US6992927B1Jan 31, 2006
Nonvolatile memory cell
NAT SEMICONDUCTOR CORP38 citations92
US6563730B1May 13, 2003
Low power static RAM architecture
NAT SEMICONDUCTOR CORP35 citations92
US6184557B1Feb 6, 2001
I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection
NAT SEMICONDUCTOR CORP40 citations92
US6169310B1Jan 2, 2001
Electrostatic discharge protection device
NAT SEMICONDUCTOR CORP34 citations92
US7558969B1Jul 7, 2009
Anti-pirate circuit for protection against commercial integrated circuit pirates
NAT SEMICONDUCTOR CORP21 citations90
US7656698B1Feb 2, 2010
Non-volatile memory cell with improved programming technique with decoupling pass gates and equalize transistors
NAT SEMICONDUCTOR CORP14 citations84
US7042763B1May 9, 2006
Programming method for nonvolatile memory cell
NAT SEMICONDUCTOR CORP18 citations84
US6262460B1Jul 17, 2001
Long channel MOS transistor that utilizes a schottky diode to increase the threshold voltage of the transistor
NAT SEMICONDUCTOR CORP18 citations84
US7164606B1Jan 16, 2007
Reverse fowler-nordheim tunneling programming for non-volatile memory cell
NAT SEMICONDUCTOR CORP17 citations83
US7206959B1Apr 17, 2007
Closed-loop, supply-adjusted ROM memory circuit
NAT SEMICONDUCTOR CORP11 citations80
US7069461B1Jun 27, 2006
Closed-loop, supply-adjusted RAM memory circuit
NAT SEMICONDUCTOR CORP11 citations80
US6618282B1Sep 9, 2003
High density ROM architecture with inversion of programming
NAT SEMICONDUCTOR CORP14 citations80
US7020027B1Mar 28, 2006
Programming method for nonvolatile memory cell
NAT SEMICONDUCTOR CORP10 citations74
US6218688B1Apr 17, 2001
Schottky diode with reduced size
NAT SEMICONDUCTOR CORP9 citations74
US6218866B1Apr 17, 2001
Semiconductor device for prevention of a floating gate condition on an input node of a MOS logic circuit and a method for its manufacture
NAT SEMICONDUCTOR CORP8 citations74
US6078094AJun 20, 2000
Starter current source device with automatic shut-down capability and method for its manufacture
NAT SEMICONDUCTOR CORP10 citations74
US6078211AJun 20, 2000
Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate
NAT SEMICONDUCTOR CORP9 citations74
US8363469B1Jan 29, 2013
All-NMOS 4-transistor non-volatile memory cell
NAT SEMICONDUCTOR CORP6 citations72
US7126866B1Oct 24, 2006
Low power ROM architecture
NAT SEMICONDUCTOR CORP10 citations72
US6642587B1Nov 4, 2003
High density ROM architecture
NAT SEMICONDUCTOR CORP10 citations72
US6285590B1Sep 4, 2001
Low power consumption semiconductor ROM, EPROM, EEPROM and like circuit
NAT SEMICONDUCTOR CORP10 citations70
US6229739B1May 8, 2001
Sense amplifier having a bias circuit with a reduced size
NAT SEMICONDUCTOR CORP4 citations63
US6049202AApr 11, 2000
Reference current generator with gated-diodes
NAT SEMICONDUCTOR CORP4 citations63
US5978269ANov 2, 1999
Apparatus and method for lowering the potential barrier across the source-to-well junction during the programming of non-volatile memory cells
NAT SEMICONDUCTOR CORP6 citations63
US7061792B1Jun 13, 2006
Low AC power SRAM architecture
NAT SEMICONDUCTOR CORP2 citations62
US6621736B1Sep 16, 2003
Method of programming a splity-gate flash memory cell with a positive inhibiting word line voltage
NAT SEMICONDUCTOR CORP4 citations61
US7453726B1Nov 18, 2008
Non-volatile memory cell with improved programming technique and density
NAT SEMICONDUCTOR CORP4 citations60
US7286383B1Oct 23, 2007
Bit line sharing and word line load reduction for low AC power SRAM architecture
NAT SEMICONDUCTOR CORP6 citations58
US6380054B1Apr 30, 2002
Schottky diode with reduced size
NAT SEMICONDUCTOR CORP0 citations52
US7602641B2Oct 13, 2009
Method of making a non-volatile memory (NVM) cell structure and program biasing techniques for the NVM cell structure
NAT SEMICONDUCTOR CORP0 citations50
POPLEVINE PAVEL
3 patentsUS8284600B1Oct 9, 2012
5-transistor non-volatile memory cell
POPLEVINE PAVEL17 citations80
US8159877B2Apr 17, 2012
Method of directly reading output voltage to determine data stored in a non-volatile memory cell
POPLEVINE PAVEL2 citations59
US8213227B2Jul 3, 2012
4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS structure
POPLEVINE PAVEL0 citations49