Anti-pirate circuit for protection against commercial integrated circuit pirates

Abstract

Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.

What is claimed is: 
     
       1. A method of enabling initial operation of an integrated circuit (IC) structure that is formed on an integrated circuit IC die, the integrated circuit IC die having an on-chip unique number generator formed thereon, the method comprising:
 prior to the initial operation of the integrated circuit IC structure, causing the on-chip unique number generator to generate a multi-bit die ID that is unique to the integrated circuit IC die; 
 storing the unique multi-bit die ID on the integrated circuit IC die as a multi-bit data string; 
 subsequent to storing the multi-bit data string on the integrated circuit IC die, causing the on-chip unique number generator to regenerate the unique multi-bit die ID; 
 comparing the regenerated unique multi-bit die ID and the stored multi-bit data string utilizing comparison circuitry that is formed on the integrated circuit IC die; and 
 generating an enable signal required for the initial operation of the integrated circuit IC structure only in the event that the comparison of the regenerated unique multi-bit die ID and the stored multi-bit data string results in match between at least a predefined number of the bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, and 
 wherein the comparing step is performed entirely on the integrated circuit IC die. 
 
     
     
       2. A The method as in  claim 1 , and wherein the storing step comprises storing the multi-bit data string in a non-volatile memory (NVM) element formed on the integrated circuit IC die. 
     
     
       3. A The method as in  claim 2 , and wherein the NVM element comprises a one-time programmable Electronically Programmable Read-Only Memory (EPROM). 
     
     
       4. A The method as in  claim 1 , ands wherein the storing step occurs at the wafer sort step in the manufacture of the integrated circuit IC die. 
     
     
       5. A The method as in  claim 1 , and wherein the step of storing the unique multi-bit die ID as the multi-bit data string comprises: encrypting the unique multi-bit die ID generated by the on-chip unique number generator to provide the multi-bit data string. 
     
     
       6. A The method as in  claim 5 , and wherein the comparing step comprises: decrypting the stored multi-bit data string for comparison with the regenerated unique multi-bit die ID. 
     
     
       7. A The method as in  claim 1 , and wherein the predefined number of bits is two or greater. 
     
     
       8. A The method as in  claim 1 , and wherein the predefined number of bits is greater than thirty-two. 
     
     
       9. A method of controlling initial operation of an integrated circuit IC that is formed on an integrated circuit IC die, the integrated circuit IC die have an on-chip unique number generator formed thereon, the method comprising:
 prior to the initial operation of the integrated circuit IC, causing the on-chip unique number generator to generate a multi-bit die ID that is unique to the integrated circuit IC die; 
 storing the unique multi-bit die ID on the integrated circuit IC die as a multi-bit data string; 
 subsequent to storing the multi-bit data string on the integrated circuit IC die, and prior to the initial operation of the integrated circuit IC, causing the on-chip unique number generator to regenerate the unique multi-bit die ID; 
 utilizing on-chip comparator circuitry formed on the integrated circuit IC die to compare the regenerated unique multi-bit die ID and the stored multi-bit data string; and 
 in the event that the comparing step results in a match equal to or greater than a predefined number of bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, providing an enable signal to the integrated circuit IC that is required for the initial operation of the integrated circuit IC; and 
 in the event that the comparing step results in a match of less than the predefined number of bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, providing a disable signal to the integrated circuit IC to disable the initial operation of the integrated circuit IC, and 
 wherein the comparing step is performed entirely on the integrated circuit IC die. 
 
     
     
       10. A The method as in  claim 9 , and wherein the disable signal permanently disables the initial operation of the integrated circuit IC. 
     
     
       11. A The method as in  claim 9 , and wherein the stored multi-bit data string is stored in a non-volatile memory (NVM) an NVM storage structure that is formed on the integrated circuit IC die. 
     
     
       12. A The method as in  claim 11 , and wherein the NVM storage structure comprises a one-time programmable EPROM. 
     
     
       13. A The method as in  claim 9 , and wherein at least a portion of the on-chip comparator circuit is embedded in the integrated circuit IC. 
     
     
       14. A The method as in  claim 9 , and wherein the storing step occurs at the wafer sort step on the manufacture of the integrated circuit IC structure. 
     
     
       15. An on-chip system for enabling the initial operation of an integrated circuit IC that is formed as part of an integrated circuit IC die, the system comprising:
 an on-chip unique number generator that is formed on the integrated circuit IC die and that generates a multi-bit die ID that is unique to the integrated circuit IC die; 
 a non-volatile memory (NVM)an NVM storage element that is formed on the integrated circuitIC die and that, prior to the initial operation of the integrated circuitIC structure, stores the unique multi-bit die ID as a stored multi-bit data string; and 
 an on-chip comparator that is formed on the integrated circuit IC die and that, prior to the initial operation of the integrated circuit IC structure, compares the unique multi-bit die ID that has been regenerated by the on-chip unique number generator and the stored multi-bit data string and that generates an enable signal required for the initial operation of the integrated circuit IC only in the event that the comparison results in a match of at least a predefined number of the bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, the entire comparison being performed on the integrated circuit IC die. 
 
     
     
       16. A The system as in  claim 15 , and wherein the NVM storage element is formed as a part of the integrated circuit IC. 
     
     
       17. A The system as in  claim 16 , and wherein the NVM storage element comprises a one-time programmable EPROM embedded in the integrated circuit IC. 
     
     
       18. A The system as in  claim 15 , and wherein at least a part of the on-chip comparator is embedded in the integrated circuit IC. 
     
     
       19. A The system as in  claim 15 , and wherein, in the event that the comparison results in a match of less than the predefined number of bits, the comparator generates a disable signal that disables the initial operation of the integrated circuit IC. 
     
     
       20. A The system as in  claim 19 , and wherein the disable signal permanently disables the initial operation of the integrated circuit IC. 
     
     
       21. An IC comprising:
 an NVM, wherein a first multi-bit number is stored in the NVM;   a number generator that is configured to generate a second multi-bit number, wherein the second multi-bit number is associated with the IC so us to operate as an identifier for the IC;   a comparator that is configured to compare corresponding bits from each of the first and second multi-bit numbers and to increment a value with each mismatch between corresponding bits from each of the first and second multi-bit numbers, wherein the comparator is configured to generate a match indicator when there is a match between a predefined number of bits of the first and second multi-bit numbers; and   logic that is configured to output an enable signal that is configured to enable functionality of at least a portion of the IC upon receiving the match indicator.   
     
     
       22. The IC of claim 21, wherein the first multi-bit number is generated and stored in the NVM at wafer sort. 
     
     
       23. The IC of claim 22, wherein the first multi-bit number is stored in a portion of the NVM that is programmable only during wafer sort. 
     
     
       24. The IC of claim 23, wherein the portion of the NVM is inaccessible outside the IC. 
     
     
       25. The IC of claim 21, wherein the predefined number further comprises a first predefined number, and wherein the portion comprise a first portion, and wherein the match indicator further comprises a first match indicator, wherein the enable signal further comprises a first enable signal, and wherein the comparator is configured to generate a second match indicator when there is a match between a second predefined number of bits of the first and second multi-bit numbers, and wherein the second predefined number of bits is greater than the first predefined number of bits, and wherein the logic is configured to generate a second enable signal that enables functionality of at least a second portion of the IC upon receiving the second match indicator. 
     
     
       26. The IC of claim 21, and wherein the output of the comparator further comprises a first output of the comparator, wherein the comparator further comprises:
 a ripple counter that is coupled to the comparator; and   a clocking circuit that is configured to clock the second multi-bit number out of the number generator serially and to clock the first multi-bit number out of the NVM serially, wherein the comparator compares one bit from each of the first and second multi-bit numbers at each clock cycle, and wherein the ripple counter is configured to be incremented each time the comparator first output indicates a mismatch.   
     
     
       27. The IC of claim 26, wherein, when the number of mismatches exceeds a predefined maximum count, the comparator is disabled. 
     
     
       28. The IC of claim 26, wherein the logic outputs the signal after the number of mismatches exceeds a predefined minimum count. 
     
     
       29. The IC of claim 21, wherein the first multi-bit number that is stored in the NVM is generated by the number generator, encrypted, and then programmed into the NVM. 
     
     
       30. The IC of claim 29, wherein the IC further comprises a decrypting circuit that is configured to selectively decrypt the first multi-bit number before the comparator performs the comparison. 
     
     
       31. A method comprising:
 generating a first multi-bit number in an IC, wherein the first multi-bit number is associated with the IC so as to operate as an identifier for the IC;   retrieving a second multi-bit number from an NVM;   in the IC, sequentially comparing corresponding bits from the first and second multi-bit numbers over a plurality of clock cycles, wherein at least one comparison is performed during each clock cycle;   incrementing a value with each mismatch between corresponding bits from each of the first and second multi-bit numbers; and   enabling functionality of at least a portion of the IC when the value reaches a predefined number.   
     
     
       32. The method of claim 31, wherein the method further comprises, at wafer sort:
 generating the second multi-bit number; and   programming the second multi-bit number into the NVM.   
     
     
       33. The method of claim 32, wherein the step of programming further comprises programming the second multi-bit number into a portion of the NVM during wafer sort, wherein the portion of the NVM has read-only accessibility following packaging. 
     
     
       34. The method of claim 31, wherein the method further comprises halting the step of sequentially comparing when the value exceeds a predefined maximum count. 
     
     
       35. The method of claim 31, wherein the method further comprises allowing the step of enabling to be performed when the value exceeds a predefined minimum count. 
     
     
       36. The method of claim 31, wherein the method further comprises:
 generating the second multi-bit number;   encrypting the second multi-bit number; and   programming the encrypted second multi-bit number into the NVM.   
     
     
       37. An IC comprising:
 an NVM;   a number generator for generating multi-bit numbers;   a multi-bit number selectively stored in the NVM;   a comparator for comparing in turn the bit value of each bit of a generated multi-bit number to the bit value of a corresponding bit of the multi-bit number stored in the NVM;   a first output from the comparator indicating whether there is a match between a first predefined number of bits of the generated multi-bit number and the stored multi-bit number;   logic configured for outputting a first signal enabling functionality of at least a first portion of the IC upon the first output indicating a match;   a second output from the comparator indicating whether there is a match between a second predefined number of bits of the generated multi-bit number and the stored multi-bit number, wherein the second predefined number of bits is greater than the first predefined number of bits; and   a second signal from the logic enabling functionality of at least a second portion of the IC upon the second output indicating a match.   
     
     
       38. An IC comprising:
 an NVM;   a number generator for generating multi-bit numbers;   a multi-bit number selectively stored in the NVM;   a comparator for comparing a generated multi-bit number to the multi-bit number stored in the NVM;   a first output from the comparator indicating whether there is a match between a first predefined number of bits of the generated multi-bit number and the stored multi-bit number;   logic configured for outputting a first signal enabling functionality of at least a first portion of the IC upon the first output indicating a match;   a ripple counter connected to the first output of the comparator; and   a clocking circuit that clocks the generated multi-bit number out of the number generator serially, and clocks the stored multi-bit number out of the NVM serially, wherein the comparator compares one bit from each of the multi-bit numbers at each clock, and wherein the ripple counter is incremented each time the first output of the comparator indicates a mismatch.   
     
     
       39. The IC of claim 38, wherein when the number of mismatches exceeds a predefined maximum count, the comparator is disabled so that the logic does not output the first signal. 
     
     
       40. The IC of claim 38, wherein the logic outputs the first signal only after the number of mismatches exceeds a predefined minimum count. 
     
     
       41. An IC comprising:
 an NVM having a first identification number stored therein, wherein the first identification number is stored in the NVM during the manufacture of the IC;   a number generator that is configured to generate a second identification number;   an identification comparator having:
 a first logic circuit that is coupled to the number generator and the NVM; 
 a ripple counter that is coupled to the first logic circuit, wherein the ripple counter is configured to count the number of mismatches between corresponding bits from each of the first and second identification numbers; and 
 a second logic circuit that is coupled to the ripple counter that is configured to generate an enable signal if there is a match between a predefined number of bits of the first and second identification numbers. 
   
     
     
       42. The IC of claim 41, wherein the first logic circuit further comprises:
 a first logic gate that is coupled to the number generator and the NVM; and   a second logic gate that is coupled to the first logic gate and the ripple counter.   
     
     
       43. The IC of claim 42, wherein the enable signal further comprises a plurality of enable signals, and wherein the second logic circuit further comprises:
 a plurality of flip-flops, wherein each flip-flop is coupled to the ripple counter; and   a set of logic gates that each output at least one of the enable signals, wherein each logic gate from the set of logic gates is coupled to at least one of the flip-flops.   
     
     
       44. The IC of claim 43, wherein the first identification number is encrypted wherein the identification comparator further comprises a decryption circuit that is coupled between the NVM and the first logic gate. 
     
     
       45. The IC of claim 44, wherein the first logic gate, the second logic gate, and each logic gate from the set of logic gates further comprises an XOR gate, a NAND gate, and a NAND gate, respectively. 
     
     
       46. The IC of claim 45, wherein each flip-flop further comprises an RS flip-flop.