Inventor

RAJA TEZASWI

US40 patents

⚠️ This page may combine multiple inventors who share the name “RAJA TEZASWI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAJA TEZASWI

NVIDIA CORP

Closed loop dynamic voltage and frequency scaling

Clock generation circuit that tracks critical path across process, voltage and temperature variation

Efficient voltage sensing systems and methods

Degradation detector and method of detecting the aging of an integrated circuit

Supply-voltage control for device power management

Protecting chips from electromagnetic pulse attacks using an antenna

Techniques for configuring a processor to execute instructions efficiently

Estimating and monitoring the effects of transistor aging

Testing system and method for in chip decoupling capacitor circuits

Circuit structures to measure flip-flop timing characteristics

Distributed digital low-dropout voltage micro regulator

Distributed digital low-dropout voltage micro regulator

Distributed digital low-dropout voltage micro regulator

Distributed digital low-dropout voltage micro regulator

On die current sink circuit for overshoot mitigation

Voltage optimization circuit and managing voltage margins of an integrated circuit

Detection of electromagnetic fault injection attacks on digital systems

Integrated current monitor

Integrated current monitor using variable drain-to-source voltages

Techniques for pre-silicon testing integrated circuit designs that accommodate power-supply noise and adaptive-clock aware timing

Overvoltage and undervoltage detector

System frequency margin recovery via distributed critical path monitors (CPM)

Technique for enabling on-die noise measurement during ate testing and IST

Voltage optimization circuit and managing voltage margins of an integrated circuit

Cross domain voltage glitch detection circuit for enhancing chip security

Low power and area clock monitoring circuit using ring delay arrangement for clock signal having phase-to-phase variation

Transient current-mode signaling scheme for on-chip interconnect fabrics

Low power and area clock monitoring circuit using a capacitor and constant current sink

Supply-voltage control for device power management

Clock generation circuit that tracks critical path across process, voltage and temperature variation

Integrated voltage regulator with in-built process, temperature and aging compensation

Integrated voltage regulator with in-built process, temperature and aging compensation

On-die techniques for asynchnorously comparing voltages

On-die techniques for converting currents to frequencies

System and method for providing low-voltage, self-powered voltage multi-sensing feedback

Adaptive voltage frequency scaling for optimal power efficiency

ZHOU TING

Interconnects using self-timed time-division multiplexed bus

AHMAD SAGHEER

Power distribution for microprocessor power gates

TANG ROBIN

Parametric data-based process monitoring for adaptive body bias control

NVIDIA CORPORTION

Selective power gating to extend the lifetime of sleep FETs