Distributed digital low-dropout voltage micro regulator

Abstract

Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a voltage regulator for accepting a first voltage and producing a regulated voltage, 
 wherein all active devices of said voltage regulator are digital devices, 
 the voltage regulator including: 
 a pulse width modulation (PWM) generator that generates a digital PWM signal, and 
 a plurality of digitally controlled power-gating header transistors, wherein the digital PWM signal is applied to at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors. 
 
     
     
       2. The integrated circuit of  claim 1  wherein all signals of said voltage regulator, except said first voltage and said regulated voltage, are characterized as digital signals. 
     
     
       3. The integrated circuit of  claim 1  wherein said plurality of digitally controlled power-gating header transistors switch said first voltage to produce said regulated voltage. 
     
     
       4. The integrated circuit of  claim 1  wherein some active devices of said voltage regulator are physically separated from other active devices of said voltage regulator by active devices of non-voltage regulator circuitry. 
     
     
       5. The integrated circuit of  claim 1  wherein said regulated voltage is configured to power a power domain, and said voltage regulator is physically within said power domain. 
     
     
       6. The integrated circuit of  claim 1  wherein the digital PWM signal is distributed to each power gate of each digitally controlled power-gating header transistor included in the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors. 
     
     
       7. The integrated circuit of  claim 6  wherein distributing the digital PWM signal to each power gate results in a phase shift in the digital PWM signal received across the digitally controlled power-gating header transistors included in the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors. 
     
     
       8. The integrated circuit of  claim 7  wherein the phase shift avoids a simultaneous state change of the digitally controlled power-gating header transistors. 
     
     
       9. The integrated circuit of  claim 1  wherein the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors represents one of a plurality of banks of the plurality of digitally controlled power-gating header transistors that, in combination, produce the regulated voltage. 
     
     
       10. The integrated circuit of  claim 9  wherein the plurality of banks are independently controlled. 
     
     
       11. The integrated circuit of  claim 10 , wherein the plurality of banks are independently controlled by independently generated digital PWM signals. 
     
     
       12. The integrated circuit of  claim 11  wherein the independently generated digital PWM signals are configurable to enable different operation of the plurality of banks. 
     
     
       13. The integrated circuit of  claim 12  wherein the operation includes being:
 turned fully off, 
 turned fully on, or 
 modulated between being turned off and turned on. 
 
     
     
       14. The integrated circuit of  claim 1  wherein the digital PWM signal applied to the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors is a non-zero duty cycle signal. 
     
     
       15. The integrated circuit of  claim 1  wherein the digital PWM signal applied to the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors causes digitally controlled power-gating header transistors included in the at least a subset two digitally controlled power-gating header transistors of the plurality of digitally controlled power-gating header transistors to modulate between being turned off and turned on.