Inventor

LIN DAHCHENG

TW22 patents

⚠️ This page may combine multiple inventors who share the name “LIN DAHCHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIN DAHCHENG

VANGUARD INT SEMICONDUCT CORP

Process to reduce defect formation occurring during shallow trench isolation formation

Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications

Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure

Process for recess-free planarization of shallow trench isolation

One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications

Method for fabricating a stacked, or crown shaped, capacitor structure

Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure

Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion

Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures

Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer

In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application

In-situ nitride and oxynitride deposition process in the same chamber

TAIWAN SEMICONDUCTOR MFG

Method of planarizing peripheral circuit region of a DRAM

Low temperature MIM capacitor for mixed-signal/RF applications

Method of manufacturing crown-shaped DRAM capacitor

TAIWAN SEMICONDUCTOR MFG CORP

Method for reading 2-bit ETOX cells using gate induced drain leakage current

Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM

Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon

WORLDWIDE SEMICONDUCTOR MANUFA

Method for fabricating a stack capacitor

Method of fabricating capacitor capable of maintaining the height of the peripheral area of the capacitor

TAIWAN SEMICONDUTOR MFG CO LTD

Method for forming contact plug

WORLDWIDE SEMICONDUCTOR MFG

Fabrication method of a twin-tub capacitor