Inventor

KEETH BRENT

US334 patents

⚠️ This page may combine multiple inventors who share the name “KEETH BRENT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KEETH BRENT

MICRON TECHNOLOGY INC

Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device

Digitline architecture for dynamic memory

Method and apparatus for bit-to-bit timing correction of a high speed memory bus

Calibration technique for memory devices

Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same

Digit line architecture for dynamic memory

High speed IC package configuration

High speed IC package configuration

Method and apparatus for adjusting the timing of signals over fine and coarse ranges

Digit line architecture for dynamic memory

Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same

Clock vernier adjustment

Synchronous clock generator including a compound delay-locked loop

Adjustable output driver circuit

Synchronous clock generator including delay-locked loop

Adjustable output driver circuit

Multi-bank memory input/output line selection

Low-skew differential signal converter

Adjustable output driver circuit having parallel pull-up and pull-down elements

Memory system with dynamic timing correction

Method and system for delay control in synchronization circuits

Method and apparatus for setting and compensating read latency in a high speed DRAM

Predictive timing calibration for memory devices

Reduced area sense amplifier isolation layout in a dynamic RAM architecture

Method of synchronizing read timing in a high speed memory system

Adjustable output driver circuit

Adjustable output driver circuit

Low skew differential receiver with disable feature

Clock vernier adjustment

Adjustable output driver circuit

Low skew differential receiver with disable feature

Method and apparatus for memory array compressed data testing

High speed input buffer

High speed input buffer

Timing calibration pattern for SLDRAM

256 Meg dynamic random access memory

256 meg dynamic random access memory

Dynamic random-access memory having a hierarchical data path

256 meg dynamic random access memory

Method of synchronizing read timing in a high speed memory system

Voltage generator with stability indicator circuit

System latency levelization for read data

Method for digit line architecture for dynamic memory

KEETH BRENT

Reconfigurable connections for stacked semiconductor devices

Stacked device identification assignment

Signal delivery in stacked device

ADVANCED MEMORY INTERNATIONAL

Memory system having synchronous-link DRAM (SLDRAM) devices and controller

MICRON TECHNNOLOGY INC

Adjustable output driver circuit having parallel pull-up and pull-down elements

(unassigned)

Dynamic random access memory having decoding circuitry for partial memory blocks

MICRON SEMICONDUCTOR INC

Control circuit responsive to its supply voltage level