Inventor · disambiguated record
Mark C. Hakey
Also filed as: HAKEY MARK C · HAKEY MARK CHARLES
228 granted patents·19 pending applications·6,248 citations·filing 1981–2022
99Inventor score
Top patents by PatentIndex Score
247 records- 0199US7528494B2Accessible chip stack and process of manufacturing thereofIBM·Filed 2005·Granted May 5, 2009·258 cites·16 claims
- 0299US7351648B2Methods for forming uniform lithographic featuresIBM·Filed 2006·Granted Apr 1, 2008·163 cites·20 claims
- 0399US6440801B1Structure for folded architecture pillar memory cellIBM·Filed 2000·Granted Aug 27, 2002·199 cites·13 claims
- 0498US8004024B2Field effect transistorIBM·Filed 2009·Granted Aug 23, 2011·106 cites·27 claims
- 0598US6875703B1Method for forming quadruple density sidewall image transfer (SIT) structuresIBM·Filed 2004·Granted Apr 5, 2005·286 cites·9 claims
- 0698US6544837B1SOI stacked DRAM logicIBM·Filed 2000·Granted Apr 8, 2003·474 cites·12 claims
- 0798US6225158B1Trench storage dynamic random access memory cell with vertical transfer deviceIBM·Filed 1998·Granted May 1, 2001·197 cites·7 claims
- 0898US6114725AStructure for folded architecture pillar memory cellIBM·Filed 1998·Granted Sep 5, 2000·160 cites·11 claims
- 0997US7256415B2Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cellsIBM·Filed 2005·Granted Aug 14, 2007·49 cites·10 claims
- 1096US7362412B2Method and apparatus for cleaning a semiconductor substrate in an immersion lithography systemIBM·Filed 2004·Granted Apr 22, 2008·62 cites·26 claims
- 1196US7351666B2Layout and process to contact sub-lithographic structuresIBM·Filed 2006·Granted Apr 1, 2008·36 cites·13 claims
- 1296US6590258B2SIO stacked DRAM logicIBM·Filed 2001·Granted Jul 8, 2003·184 cites·12 claims
- 1395US6506660B2Semiconductor with nanoscale featuresIBM·Filed 2001·Granted Jan 14, 2003·101 cites·18 claims
- 1495US6387783B1Methods of T-gate fabrication using a hybrid resistIBM·Filed 1999·Granted May 14, 2002·134 cites·18 claims
- 1595US6338934B1Hybrid resist based on photo acid/photo base blendingIBM·Filed 1999·Granted Jan 15, 2002·126 cites·29 claims
- 1695US6096598AMethod for forming pillar memory cells and device formed therebyIBM·Filed 1998·Granted Aug 1, 2000·200 cites·23 claims
- 1795US5945707ADRAM cell with grooved transfer deviceIBM·Filed 1998·Granted Aug 31, 1999·127 cites·15 claims
- 1894US7691720B2Vertical nanotube semiconductor device structures and methods of forming the sameIBM·Filed 2007·Granted Apr 6, 2010·22 cites·17 claims
- 1994US7607455B2Micro-electro-mechanical valves and pumps and methods of fabricating sameIBM·Filed 2008·Granted Oct 27, 2009·21 cites·39 claims
- 2094US7535016B2Vertical carbon nanotube transistor integrationIBM·Filed 2005·Granted May 19, 2009·33 cites·20 claims
- 2194US7473633B2Method for making integrated circuit chip having carbon nanotube composite interconnection viasIBM·Filed 2006·Granted Jan 6, 2009·29 cites·18 claims
- 2294US7265013B2Sidewall image transfer (SIT) technologiesIBM·Filed 2005·Granted Sep 4, 2007·25 cites·30 claims
- 2394US7071047B1Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regionsIBM·Filed 2005·Granted Jul 4, 2006·19 cites·34 claims
- 2493US7483285B2Memory devices using carbon nanotube (CNT) technologiesIBM·Filed 2008·Granted Jan 27, 2009·27 cites·14 claims
- 2593US7358120B2Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROMIBM·Filed 2007·Granted Apr 15, 2008·25 cites·22 claims
- 2693US6891235B1FET with T-shaped gateIBM·Filed 2000·Granted May 10, 2005·56 cites·20 claims
- 2793US6627477B1Method of assembling a plurality of semiconductor devices having different thicknessIBM·Filed 2000·Granted Sep 30, 2003·68 cites·26 claims
- 2893US5831301ATrench storage dram cell including a step transfer deviceIBM·Filed 1998·Granted Nov 3, 1998·80 cites·8 claims
- 2992US6037194AMethod for making a DRAM cell with grooved transfer deviceIBM·Filed 1999·Granted Mar 14, 2000·82 cites·35 claims
- 3091US6358813B1Method for increasing the capacitance of a semiconductor capacitorsIBM·Filed 2000·Granted Mar 19, 2002·56 cites·30 claims
- 3191US6107133AMethod for making a five square vertical DRAM cellIBM·Filed 1998·Granted Aug 22, 2000·71 cites·6 claims
- 3290US8039334B2Shared gate for conventional planar device and horizontal CNTIBM·Filed 2010·Granted Oct 18, 2011·10 cites·15 claims
- 3390US7352607B2Non-volatile switching and memory devices using vertical nanotubesIBM·Filed 2005·Granted Apr 1, 2008·21 cites·8 claims
- 3489US7922796B2Chemical and particulate filters containing chemically modified carbon nanotube structuresIBM·Filed 2010·Granted Apr 12, 2011·4 cites·10 claims
- 3589US7674674B2Method of forming a dual gated FinFET gain cellIBM·Filed 2008·Granted Mar 9, 2010·13 cites·10 claims
- 3689US7491631B2Method of doping a gate electrode of a field effect transistorIBM·Filed 2007·Granted Feb 17, 2009·11 cites·13 claims
- 3789US7135773B2Integrated circuit chip utilizing carbon nanotube composite interconnection viasIBM·Filed 2004·Granted Nov 14, 2006·49 cites·17 claims
- 3889US6970372B1Dual gated finfet gain cellIBM·Filed 2004·Granted Nov 29, 2005·37 cites·18 claims
- 3989US6184151B1Method for forming cornered images on a substrate and photomask formed therebyIBM·Filed 1999·Granted Feb 6, 2001·92 cites·17 claims
- 4089US6121651ADram cell with three-sided-gate transfer deviceIBM·Filed 1998·Granted Sep 19, 2000·68 cites·20 claims
- 4189US6114082AFrequency doubling hybrid photoresist having negative and positive tone components and method of preparing the sameIBM·Filed 1996·Granted Sep 5, 2000·81 cites·21 claims
- 4288US7233071B2Low-k dielectric layer based upon carbon nanostructuresIBM·Filed 2004·Granted Jun 19, 2007·33 cites·14 claims
- 4388US7229889B2Methods for metal plating of gate conductors and semiconductors formed therebyIBM·Filed 2005·Granted Jun 12, 2007·14 cites·17 claims
- 4488US6531724B1Borderless gate structuresIBM·Filed 2000·Granted Mar 11, 2003·37 cites·8 claims
- 4588US6489207B2Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductorIBM·Filed 2001·Granted Dec 3, 2002·38 cites·9 claims
- 4688US6429045B1Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damageIBM·Filed 2001·Granted Aug 6, 2002·74 cites·15 claims
- 4788US6190988B1Method for a controlled bottle trench for a dram storage nodeIBM·Filed 1998·Granted Feb 20, 2001·64 cites·22 claims
- 4887US7708816B2Chemical and particulate filters containing chemically modified carbon nanotube structuresIBM·Filed 2008·Granted May 4, 2010·6 cites·13 claims
- 4987US7566613B2Method of forming a dual gated FinFET gain cellIBM·Filed 2005·Granted Jul 28, 2009·11 cites·13 claims
- 5087US7484423B2Integrated carbon nanotube sensorsIBM·Filed 2007·Granted Feb 3, 2009·12 cites·19 claims
Showing the top 50 of 247 patent records by PatentIndex Score.
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