Assignee
FURUKAWA TOSHIHARU
US·6 granted patents·4 pending applications·17 citations·filing 2004–2012
Top patents by PatentIndex Score
10 records- 0186US8610211B2Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structureFURUKAWA TOSHIHARU·Filed 2010·Granted Dec 17, 2013·6 cites·20 claims
- 0275US8183159B2Device component forming method with a trim step prior to sidewall image transfer (SIT) processingFURUKAWA TOSHIHARU·Filed 2008·Granted May 22, 2012·4 cites·11 claims
- 0372US8138100B2Microelectronic structure by selective depositionFURUKAWA TOSHIHARU·Filed 2008·Granted Mar 20, 2012·3 cites·10 claims
- 0471US8541823B2Field effect transistorFURUKAWA TOSHIHARU·Filed 2011·Granted Sep 24, 2013·2 cites·18 claims
- 0555US2008128811A1Semiconductor devices with buried isolation regionsFURUKAWA TOSHIHARU·Filed 2008·Application pending·0 cites
- 0653US8697561B2Microelectronic structure by selective depositionFURUKAWA TOSHIHARU·Filed 2012·Granted Apr 15, 2014·0 cites·19 claims
- 0751US2012208356A1Device component forming method with a trim step prior to sidewall image transfer (SIT) processingFURUKAWA TOSHIHARU·Filed 2012·Application pending·0 cites
- 0848US8450806B2Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed therebyFURUKAWA TOSHIHARU·Filed 2004·Granted May 28, 2013·2 cites·14 claims
- 0943US2008217730A1Methods of forming gas dielectric and related structureFURUKAWA TOSHIHARU·Filed 2007·Application pending·0 cites
- 1042US2008085600A1Method of forming lithographic and sub-lithographic dimensioned structuresFURUKAWA TOSHIHARU·Filed 2006·Application pending·0 cites
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