Device component forming method with a trim step prior to sidewall image transfer (SIT) processing

Abstract

Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.

1 . An imaging method for forming device components in a substrate, said method comprising:
 forming multiple layers above a substrate, wherein said multiple layers comprise a first mask layer above said substrate and a trim mask layer above said first mask layer;   trimming at least one of said multiple layers using said trim mask; and   after said trimming of said at least one of said multiple layers, patterning said first mask layer with at least one discrete segment.   
     
     
         2 . The method of  claim 1 , wherein by patterning said first mask layer, after said trimming of said at least one of said multiple layers, said method avoids a subsequent trim process that requires alignment to a feature in said first mask layer that has less than current state of the art minimum lithographic dimensions using a sidewall image transfer process. 
     
     
         3 . The method of  claim 1 , wherein said patterning of said first mask layer comprises using one of an additive sidewall image transfer process and a subtractive sidewall image transfer process. 
     
     
         4 . The method of  claim 1 , further comprising forming said substrate with a silicon layer and etching said pattern into said substrate to form at least one silicon fin for a fin-type field effect transistor. 
     
     
         5 . The method of  claim 1 , wherein by performing said sidewall image transfer process after said trimming of said at least one of said multiple layers, said method avoids a subsequent trim process that requires alignment to a feature in said hard mask layer that has less than current state of the art minimum lithographic dimensions. 
     
     
         7 . An imaging method for forming device components in a substrate, said method comprising:
 forming multiple layers above a substrate, said multiple layers comprising at least a hard mask layer on said substrate and a trim mask layer above said hard mask layer;   lithographically patterning said trim mask layer into a trim mask and using said trim mask during an etch process to trim end portions of at least one of said multiple layers;   after said etch process to trim end portions of at least one of said multiple layers, removing said trim mask; and   after said removing of said trim mask and before any etching of said substrate, using a sidewall image transfer process to form, from said hard mask layer, a hard mask pattern comprising at least two discrete parallel rectangular-shaped hard mask segments on said substrate.   
     
     
         8 . The method of  claim 7 , said using of said sidewall image transfer process after said etch process to trim at least one of said multiple layers avoids the formation of a loop-shaped hard mask segment. 
     
     
         9 . The method of  claim 8 , wherein avoidance of said formation of said loop-shaped hard mask segment avoids a subsequent etch process to trim said loop-shaped hard mask segment into said two discrete parallel rectangular-shaped hard mask segments, said subsequent etch process requiring trim mask alignment to features having less than current state of the art minimum lithographic dimensions. 
     
     
         10 . The method of  claim 7 , said sidewall image transfer process comprising any one of an additive sidewall image transfer process and a subtractive sidewall image transfer process. 
     
     
         11 . The method of  claim 7 , said substrate comprising a silicon layer and said method further comprising using said hard mask pattern during an additional etch process to pattern, from said silicon layer, at least two silicon fins for at least one fin-type field effect transistor. 
     
     
         12 . The method of  claim 7 , further comprising:
 forming said substrate with an active silicon region, a dielectric layer on said active silicon region and a conductor layer on said dielectric layer;   aligning said second mask layer with said active silicon region before trimming said at least one of said multiple layers; and   etching said pattern into said conductor layer to form at least one gate electrodes on said dielectric layer.   
     
     
         13 . The method of  claim 7 , said lithographically patterning of said trim mask layer comprising aligning said trim mask to a feature in said substrate. 
     
     
         14 . An imaging method for forming device components in a substrate, said method comprising:
 providing a substrate comprising a silicon layer;   forming multiple layers above said substrate, said multiple layers comprising at least a hard mask layer on said silicon layer and a trim mask layer above said hard mask layer;   lithographically patterning said trim mask layer into a trim mask and using said trim mask during an etch process to trim end portions of at least one of said multiple layers;   after said etch process to trim end portions of at least one of said multiple layers, removing said trim mask;   after said removing of said trim mask and before any etching of said substrate, using a sidewall image transfer process to form, from said hard mask layer, a hard mask pattern comprising at least two discrete parallel rectangular-shaped hard mask segments on said substrate; and   using said hard mask pattern during an additional etch process to pattern, from said silicon layer, at least two silicon fins for at least one fin-type field effect transistor.   
     
     
         15 . The method of  claim 14 , said using of said sidewall image transfer process after said etch process to trim at least one of said multiple layers avoids the formation of a loop-shaped hard mask segment. 
     
     
         16 . The method of  claim 15 , wherein avoidance of said formation of said loop-shaped hard mask segment avoids a subsequent etch process to trim said loop-shaped hard mask segment into said two discrete parallel rectangular-shaped hard mask segments, said subsequent etch process requiring trim mask alignment to features having less than current state of the art minimum lithographic dimensions. 
     
     
         17 . The method of  claim 14 , said sidewall image transfer process comprising any one of an additive sidewall image transfer process and a subtractive sidewall image transfer process. 
     
     
         18 . The method of  claim 14 , said substrate comprising a silicon layer and said method further comprising using said hard mask pattern during an additional etch process to pattern, from said silicon layer, at least two silicon fins for at least one fin-type field effect transistor. 
     
     
         19 . The method of  claim 14 , said lithographically patterning of said trim mask layer comprising aligning said trim mask to a feature in said substrate.