Inventor · disambiguated record
Charles W. Koburger, Iii
Also filed as: KOBURGER CHARLES W · KOBURGER CHARLES W III · KOBURGER CHARLES WILLIAM · KOBURGER III CHARLES
219 granted patents·26 pending applications·4,009 citations·filing 1981–2016
99Inventor score
Files withIBM192GLOBALFOUNDRIES INC8FURUKAWA TOSHIHARU7KOBURGER III CHARLES W6BASKER VEERARAGHAVAN S5
Top patents by PatentIndex Score
245 records- 0199US7528494B2Accessible chip stack and process of manufacturing thereofIBM·Filed 2005·Granted May 5, 2009·258 cites·16 claims
- 0299US7351648B2Methods for forming uniform lithographic featuresIBM·Filed 2006·Granted Apr 1, 2008·163 cites·20 claims
- 0399US7084060B1Forming capping layer over metal wire structure using selective atomic layer depositionIBM·Filed 2005·Granted Aug 1, 2006·637 cites·16 claims
- 0498US8785284B1FinFETs and fin isolation structuresIBM·Filed 2013·Granted Jul 22, 2014·34 cites·18 claims
- 0598US8004024B2Field effect transistorIBM·Filed 2009·Granted Aug 23, 2011·106 cites·27 claims
- 0698US6875703B1Method for forming quadruple density sidewall image transfer (SIT) structuresIBM·Filed 2004·Granted Apr 5, 2005·286 cites·9 claims
- 0798US6713835B1Method for manufacturing a multi-level interconnect structureIBM·Filed 2003·Granted Mar 30, 2004·297 cites·39 claims
- 0897US8299625B2Borderless interconnect line structure self-aligned to upper and lower level contact viasPONOTH SHOM·Filed 2010·Granted Oct 30, 2012·45 cites·11 claims
- 0997US7256415B2Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cellsIBM·Filed 2005·Granted Aug 14, 2007·49 cites·10 claims
- 1096US9177820B2Sub-lithographic semiconductor structures with non-constant pitchIBM·Filed 2012·Granted Nov 3, 2015·20 cites·12 claims
- 1196US8906807B2Single fin cut employing angled processing methodsIBM·Filed 2012·Granted Dec 9, 2014·23 cites·20 claims
- 1296US8492274B2Metal alloy cap integrationIBM·Filed 2012·Granted Jul 23, 2013·19 cites·9 claims
- 1396US8390079B2Sealed air gap for semiconductor chipHORAK DAVID V·Filed 2010·Granted Mar 5, 2013·26 cites·4 claims
- 1496US8232618B2Semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device and a method of forming the semiconductor structure using a self-assembly approachBREYTA GREGORY·Filed 2010·Granted Jul 31, 2012·33 cites·12 claims
- 1596US7351666B2Layout and process to contact sub-lithographic structuresIBM·Filed 2006·Granted Apr 1, 2008·36 cites·13 claims
- 1696US7276768B2Semiconductor structures for latch-up suppression and methods of forming such semiconductor structuresIBM·Filed 2006·Granted Oct 2, 2007·30 cites·8 claims
- 1795US9040363B2FinFET with reduced capacitanceIBM·Filed 2013·Granted May 26, 2015·12 cites·19 claims
- 1895US8896067B2Method of forming finFET of variable channel widthIBM·Filed 2013·Granted Nov 25, 2014·20 cites·13 claims
- 1995US8471343B2Parasitic capacitance reduction in MOSFET by airgap ildDORIS BRUCE B·Filed 2011·Granted Jun 25, 2013·23 cites·24 claims
- 2094US9263290B2Sub-lithographic semiconductor structures with non-constant pitchGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 16, 2016·8 cites·7 claims
- 2194US8525339B2Hybrid copper interconnect structure and method of fabricating sameYANG CHIH-CHAO·Filed 2011·Granted Sep 3, 2013·16 cites·16 claims
- 2294US7691720B2Vertical nanotube semiconductor device structures and methods of forming the sameIBM·Filed 2007·Granted Apr 6, 2010·22 cites·17 claims
- 2394US7607455B2Micro-electro-mechanical valves and pumps and methods of fabricating sameIBM·Filed 2008·Granted Oct 27, 2009·21 cites·39 claims
- 2494US7535016B2Vertical carbon nanotube transistor integrationIBM·Filed 2005·Granted May 19, 2009·33 cites·20 claims
- 2594US7473633B2Method for making integrated circuit chip having carbon nanotube composite interconnection viasIBM·Filed 2006·Granted Jan 6, 2009·29 cites·18 claims
- 2694US7265013B2Sidewall image transfer (SIT) technologiesIBM·Filed 2005·Granted Sep 4, 2007·25 cites·30 claims
- 2794US7071047B1Method of forming buried isolation regions in semiconductor substrates and semiconductor devices with buried isolation regionsIBM·Filed 2005·Granted Jul 4, 2006·19 cites·34 claims
- 2893US9196613B2Stress inducing contact metal in FinFET CMOSIBM·Filed 2013·Granted Nov 24, 2015·13 cites·6 claims
- 2993US8941156B2Self-aligned dielectric isolation for FinFET devicesIBM·Filed 2013·Granted Jan 27, 2015·13 cites·16 claims
- 3093US7521776B2Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centersIBM·Filed 2006·Granted Apr 21, 2009·24 cites·1 claims
- 3193US7483285B2Memory devices using carbon nanotube (CNT) technologiesIBM·Filed 2008·Granted Jan 27, 2009·27 cites·14 claims
- 3293US7358120B2Silicon-on-insulator (SOI) read only memory (ROM) array and method of making a SOI ROMIBM·Filed 2007·Granted Apr 15, 2008·25 cites·22 claims
- 3393US6531375B1Method of forming a body contact using BOX modificationIBM·Filed 2001·Granted Mar 11, 2003·78 cites·13 claims
- 3492US8835305B2Method of fabricating a profile control in interconnect structuresYANG CHIH-CHAO·Filed 2012·Granted Sep 16, 2014·12 cites·13 claims
- 3592US8368146B2FinFET devicesIBM·Filed 2010·Granted Feb 5, 2013·12 cites·7 claims
- 3692US7381655B2Mandrel/trim alignment in SIT processingIBM·Filed 2005·Granted Jun 3, 2008·15 cites·6 claims
- 3791US8828876B2Dual mandrel sidewall image transfer processesIBM·Filed 2013·Granted Sep 9, 2014·10 cites·19 claims
- 3891US8030202B1Temporary etchable liner for forming air gapIBM·Filed 2010·Granted Oct 4, 2011·13 cites·20 claims
- 3991US7510939B2Microelectronic structure by selective depositionIBM·Filed 2006·Granted Mar 31, 2009·15 cites·1 claims
- 4090US8039334B2Shared gate for conventional planar device and horizontal CNTIBM·Filed 2010·Granted Oct 18, 2011·10 cites·15 claims
- 4190US7352607B2Non-volatile switching and memory devices using vertical nanotubesIBM·Filed 2005·Granted Apr 1, 2008·21 cites·8 claims
- 4290US7329613B2Structure and method for forming semiconductor wiring levels using atomic layer depositionIBM·Filed 2005·Granted Feb 12, 2008·15 cites·17 claims
- 4390US6498096B2Borderless contact to diffusion with respect to gate conductor and methods for fabricatingIBM·Filed 2001·Granted Dec 24, 2002·62 cites·11 claims
- 4489US8871624B2Sealed air gap for semiconductor chipIBM·Filed 2013·Granted Oct 28, 2014·8 cites·15 claims
- 4589US8735279B2Air-dielectric for subtractive etch line and via metallizationHORAK DAVID V·Filed 2011·Granted May 27, 2014·9 cites·14 claims
- 4689US7674674B2Method of forming a dual gated FinFET gain cellIBM·Filed 2008·Granted Mar 9, 2010·13 cites·10 claims
- 4789US7491631B2Method of doping a gate electrode of a field effect transistorIBM·Filed 2007·Granted Feb 17, 2009·11 cites·13 claims
- 4889US7135773B2Integrated circuit chip utilizing carbon nanotube composite interconnection viasIBM·Filed 2004·Granted Nov 14, 2006·49 cites·17 claims
- 4989US6970372B1Dual gated finfet gain cellIBM·Filed 2004·Granted Nov 29, 2005·37 cites·18 claims
- 5088US8629511B2Mask free protection of work function material portions in wide replacement gate electrodesKOBURGER III CHARLES W·Filed 2012·Granted Jan 14, 2014·10 cites·16 claims
Showing the top 50 of 245 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →