Inventor

MORROW PATRICK

US187 patents

⚠️ This page may combine multiple inventors who share the name “MORROW PATRICK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MORROW PATRICK

INTEL CORP

Stacked device underfill and a method of fabrication

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

MOS transistor structure and method of fabrication

Methods of forming backside connections on a wafer stack

Methods of forming backside connections on a wafer stack

Method for making a dual damascene interconnect using a multilayer hard mask

Portable NMR device and method for making and using the same

Integrated on-chip NMR and ESR device and method for making and using the same

Field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Methods of making field effect transistor structure with partially isolated source/drain junctions

Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Methods of forming backside self-aligned vias and structures formed thereby

Monolithic three-dimensional (3D) ICs with local inter-level interconnects

MOS transistor structure and method of fabrication

Integrated circuit structures

Laminating magnetic materials in a semiconductor device

Method of making semiconductor device using a novel interconnect cladding layer

Bonded wafer processing method

Semiconductor device having a dual damascene interconnect spaced from a support structure

Forksheet transistor architectures

Backside contact structures and fabrication for metal on both sides of devices

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Fabrication and use of through silicon vias on double sided interconnect device

Wrap-around source/drain method of making contacts for backside metals

Fabrication and use of through silicon vias on double sided interconnect device

Integrated circuit device with crenellated metal trace layout

Composite IC chips including a chiplet embedded within metallization layers of a host IC chip

Integrated circuit layout using library cells with alternating conductive lines

Methods of forming backside self-aligned vias and structures formed thereby

Metal on both sides with power distributed through the silicon

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

Monolithic three-dimensional (3D) ICs with local inter-level interconnects

Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)

Techniques for forming vertical transistor architectures

Method for making a dual damascene interconnect using a dual hard mask

Three-dimensional stacked substrate arrangements

Dual-damascene interconnects without an etch stop layer by alternating ILDs

Stacked forksheet transistors

Sealed three dimensional metal bonded integrated circuits

Microelectronic assemblies

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

Interconnect techniques for electrically connecting source/drain regions of stacked transistors

Stacked transistors having device strata with different channel widths

RAMANATHAN SHRIRAM

Three-dimensional stacked substrate arrangements

MA QING

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

MURTHY ANAND S

Field effect transistor structure with abrupt source/drain junctions