Inventor

WOO STEVEN C

US72 patents

⚠️ This page may combine multiple inventors who share the name “WOO STEVEN C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOO STEVEN C

RAMBUS INC

Memory controller with power management logic

Methods and systems for reducing heat flux in memory systems

Apparatus and method for thermal regulation in memory subsystems

Apparatus and method for thermal regulation in memory subsystems

Consolidation of allocated memory to reduce power consumption

Methods and systems for reducing heat flux in memory systems

Methods and systems for reducing heat flux in memory systems

Method and apparatus for calibrating write timing in a memory system

System and method for improving performance in computer memory systems supporting multiple memory access latencies

Consolidation of allocated memory to reduce power consumption

Memory controller with power management logic

High-bandwidth neural network

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Communication via a memory interface

Memory controller with prefetching capability

Methods and circuits for streaming data to processing elements in stacked processor-plus-memory architecture

Method and apparatus for calibrating write timing in a memory system

Methods and systems for reducing heat flux in memory systems

Memory controller with power management logic

Interconnect based address mapping for improved reliability

Method and apparatus for calibrating write timing in a memory system

Multi-modal refresh of dynamic, random-access memory

Quad-channel DRAM

Method and apparatus for calibrating write timing in a memory system

Data buffer for memory devices with memory address remapping

Stacked device system

High-bandwidth neural network

Quad-channel DRAM

Stacked device system

Method and apparatus for calibrating write timing in a memory system

Securing address information in a memory controller

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Atomic-operation coalescing technique in multi-chip systems

Buffer device with low-latency skid mode for data freshness

Memory device having hidden refresh

DRAM cache with stacked, heterogenous tag and data dies

Stacked device communication

Page table manager

Multi-modal refresh of dynamic, random-access memory

GIOVANNINI THOMAS J

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

HUGHES AIRCRAFT CO

Method and parallel processor computing apparatus for determining the three-dimensional coordinates of objects using data from two-dimensional sensors

Neural engine for emulating a neural network

CRYPTOGRAPHY RES INC

Authentication of a device

Authentication of a device

WOO STEVEN C

Selective switching of a memory bus

LIN QI

Atomic-operation coalescing technique in multi-chip systems