Inventor

TSUKUDE MASAKI

JP116 patents

⚠️ This page may combine multiple inventors who share the name “TSUKUDE MASAKI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSUKUDE MASAKI

MITSUBISHI ELECTRIC CORP

Switched backgate bias for FET

Semiconductor integrated circuit device having hierarchical power source arrangement

Sense amplifier including MOS transistors having threshold voltages controlled dynamically in a semiconductor memory device

Switched substrate bias for logic circuits

Dynamic semiconductor memory device of a twisted bit line system having improved reliability of readout

Synchronous dynamic semiconductor memory device capable of restricting delay of data output timing

Semiconductor memory device having a redundant row and a redundant column which can be accessed prior to substitution

Synchronous semiconductor memory device having a plurality of banks distributed in a plurality of memory arrays

Switched substrate bias for MOS-DRAM circuits

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor integrated circuit

Semiconductor integrated circuit device having hierarchical power source arrangement

Voltage supply circuit and semiconductor device including such circuit

Semiconductor integrated circuit device having hierarchical power source arrangement

Column selecting circuit in semiconductor memory device

Switched substrate bias for MOS DRAM circuits

Arrangement of power supply and data input/output pads in semiconductor memory device

Semiconductor memory device

Semiconductor memory device with an improved hierarchical power supply line configuration

Arrangement of power supply and data input/output pads in semiconductor memory device

Semiconductor memory device having self-refreshing function

Semiconductor device incorporating internal voltage down converting circuit

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor memory device of low power consumption

Semiconductor memory device

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor integrated circuit device having hierarchical power source arrangement

Semiconductor memory device having burn-in mode operation stably accelerated

Semiconductor memory device having a pad arrangement with reduced occupying area

Semiconductor memory device having burn-in mode operation stably accelerated

Voltage supply circuit and semiconductor device including such circuit

Semiconductor device comprising a plurality of interconnection patterns

Semiconductor memory device having hierarchical word line structure

Semiconductor memory device having burn-in mode operation stably accelerated

Semiconductor memory device

Semiconductor memory device capable of burn in mode operation

Memory device and sense amplifier control device

Semiconductor integrated circuit device having stable input protection circuit

Semiconductor memory device allowing writing of desired data to a storage node of a defective memory cell

Semiconductor memory device with an improved hierarchical power supply line configuration

Semiconductor device having a fuse and an improved moisture resistance

Semiconductor memory device having hierarchical bit line structure

Constant current generating circuit

Semiconductor memory device provided with sense amplifier capable of high speed operation with low power consumption

Semiconductor integrated circuit device having a test mode for reliability evaluation

Hierarchical bit line arrangement in a semiconductor memory

Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system

Semiconductor memory device

RENESAS TECH CORP

Semiconductor memory device with activation of a burst refresh when a long cycle is detected

Semiconductor memory device having refresh circuit