Inventor · disambiguated record
Shreepad Amar Panth
Also filed as: PANTH SHREEPAD · PANTH SHREEPAD A · PANTH SHREEPAD AMAR
7 granted patents·1 pending application·24 citations·filing 2013–2019
81Inventor score
Top patents by PatentIndex Score
8 records- 0187US9098666B2Clock distribution network for 3D integrated circuitQUALCOMM INC·Filed 2013·Granted Aug 4, 2015·8 cites·24 claims
- 0283US10770443B2Clock architecture in heterogeneous system-in-packageINTEL CORP·Filed 2018·Granted Sep 8, 2020·4 cites·22 claims
- 0382US9123721B2Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespaceQUALCOMM INC·Filed 2013·Granted Sep 1, 2015·5 cites·15 claims
- 0477US9064077B23D floorplanning using 2D and 3D blocksQUALCOMM INC·Filed 2013·Granted Jun 23, 2015·5 cites·18 claims
- 0573US10510651B2Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macroQUALCOMM INC·Filed 2018·Granted Dec 17, 2019·1 cites·6 claims
- 0663US11004780B2Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macroQUALCOMM INC·Filed 2019·Granted May 11, 2021·0 cites·19 claims
- 0763US10192813B2Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macroQUALCOMM INC·Filed 2013·Granted Jan 29, 2019·1 cites·17 claims
- 0844US2015333005A1PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACQUALCOMM INC·Filed 2015·Application pending·0 cites
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