PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC

Abstract

Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

What is claimed is: 
     
         1 . A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
 a plurality of IC tiers;   a plurality of IC blocks each disposed in an IC tier among the plurality of IC tiers; and   a plurality of Monolithic Inter-tier Vias (MIVs) disposed across at least two IC tiers among the plurality of IC tiers to interconnect at least two IC blocks among the plurality of IC blocks;   wherein at least ten percent (10%) of the plurality of MIVs comprises at least two MIVs aligned within a two-dimensional (2D) section of the monolithic 3DIC.   
     
     
         2 . The monolithic 3DIC of  claim 1 , wherein the 2D section of the monolithic 3DIC comprises a row within the monolithic 3DIC. 
     
     
         3 . The monolithic 3DIC of  claim 1 , wherein the 2D section of the monolithic 3DIC comprises a column within the monolithic 3DIC. 
     
     
         4 . The monolithic 3DIC of  claim 1 , wherein the at least ten percent (10%) of the plurality of MIVs further comprises the at least two MIVs clustered into a corresponding MIV placement cluster of one or more MIV placement clusters. 
     
     
         5 . The monolithic 3DIC of  claim 4 , wherein each of the one of more MIV placement clusters has a radius of at least twenty (20) transistor gate pitches. 
     
     
         6 . The monolithic 3DIC of  claim 4 , further comprising a usable whitespace between the one or more MIV placement clusters, wherein one or more buffers are placed within the usable whitespace for timing optimization. 
     
     
         7 . The monolithic 3DIC of  claim 1 , wherein each IC block of the plurality of IC blocks comprises a standard cell. 
     
     
         8 . The monolithic 3DIC of  claim 1 , wherein each IC block of the plurality of IC blocks comprises an IC logic gate. 
     
     
         9 . The monolithic 3DIC of  claim 1  provided in a semiconductor die. 
     
     
         10 . The monolithic 3DIC of  claim 1  integrated into a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player. 
     
     
         11 . A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
 a means for providing a plurality of IC tiers;   a means for providing a plurality of IC blocks each disposed in an IC tier among the means for providing the plurality of IC tiers; and   a means for providing a plurality of Monolithic Inter-tier Vias (MIVs) disposed across at least two IC tiers among the means for providing the plurality of IC tiers, for interconnecting at least two IC blocks among the means for providing the plurality of IC blocks;   wherein at least ten percent (10%) of the means for providing the plurality of MIVs comprises at least two MIVs aligned within a two-dimensional (2D) section of the monolithic 3DIC.   
     
     
         12 . A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
 a plurality of IC tiers;   a plurality of IC blocks each disposed in an IC tier among the plurality of IC tiers;   a plurality of Monolithic Inter-tier Vias (MIVs) disposed across at least two IC tiers among the plurality of IC tiers to interconnect at least two IC blocks among the plurality of IC blocks; and   at least two MIV placement clusters, wherein the plurality of MIVs within the at least two MIV placement clusters are placed so that at least three two-dimensional (2D) sections within the monolithic 3DIC have aligned MIVs.   
     
     
         13 . The monolithic 3DIC of  claim 12 , wherein each 2D section of the at least three 2D sections of the monolithic 3DIC comprises a row within the monolithic 3DIC. 
     
     
         14 . The monolithic 3DIC of  claim 12 , wherein each 2D section of the at least three 2D sections of the monolithic 3DIC comprises a column within the monolithic 3DIC. 
     
     
         15 . The monolithic 3DIC of  claim 12 , wherein the plurality of MIVs within each of the at least two MIV placement clusters has a total area equal to or less than an area of a corresponding MIV placement cluster of the at least two MIV placement clusters. 
     
     
         16 . The monolithic 3DIC of  claim 12 , wherein each of the at least two MIV placement clusters has a radius of at least twenty (20) transistor gate pitches. 
     
     
         17 . The monolithic 3DIC of  claim 12 , further comprising a usable whitespace between the at least two MIV placement clusters, wherein one or more buffers are placed within the usable whitespace for timing optimization. 
     
     
         18 . The monolithic 3DIC of  claim 12 , wherein each IC block of the plurality of IC blocks comprises a standard cell. 
     
     
         19 . The monolithic 3DIC of  claim 12 , wherein each IC block of the plurality of IC blocks comprises an IC logic gate. 
     
     
         20 . The monolithic 3DIC of  claim 12  provided in a semiconductor die. 
     
     
         21 . The monolithic 3DIC of  claim 12  integrated into a device selected from the group consisting of a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player. 
     
     
         22 . A monolithic three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
 a means for providing a plurality of IC tiers;   a means for providing a plurality of IC blocks each disposed in an IC tier among the means for providing the plurality of IC tiers;   a means for providing a plurality of Monolithic Inter-tier Vias (MIVs) disposed across at least two IC tiers among the means for providing the plurality of IC tiers, for interconnecting at least two IC blocks among the means for providing the plurality of IC blocks; and   a means for providing at least two MIV placement clusters, wherein the means for providing the plurality of MIVs within the means for providing the at least two MIV placement clusters are placed so that at least three two-dimensional (2D) sections within the monolithic 3DIC have aligned MIVs.