Inventor · disambiguated record
Pratyush Kamal
Also filed as: KAMAL PRATYUSH
16 granted patents·6 pending applications·126 citations·filing 2011–2020
92Inventor score
Top patents by PatentIndex Score
22 records- 0198US11444068B2Three-dimensional (3D) integrated circuit device having a backside power delivery networkQUALCOMM INC·Filed 2020·Granted Sep 13, 2022·15 cites·10 claims
- 0297US10121743B2Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)QUALCOMM INC·Filed 2017·Granted Nov 6, 2018·31 cites·16 claims
- 0397US9754923B1Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)QUALCOMM INC·Filed 2016·Granted Sep 5, 2017·30 cites·16 claims
- 0493US8836040B2Shared-diffusion standard cell architectureQUALCOMM INC·Filed 2012·Granted Sep 16, 2014·17 cites·20 claims
- 0584US9147438B2Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methodsQUALCOMM INC·Filed 2014·Granted Sep 29, 2015·7 cites·21 claims
- 0682US9123721B2Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespaceQUALCOMM INC·Filed 2013·Granted Sep 1, 2015·5 cites·15 claims
- 0781US9013235B2Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methodsQUALCOMM INC·Filed 2013·Granted Apr 21, 2015·5 cites·20 claims
- 0877US8584075B2Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristicsDATTA ANIMESH·Filed 2011·Granted Nov 12, 2013·6 cites·94 claims
- 0973US9213358B2Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related componentsQUALCOMM INC·Filed 2014·Granted Dec 15, 2015·3 cites·15 claims
- 1071US8610176B2Standard cell architecture using double poly patterning for multi VT devicesPATEL PRAYAG B·Filed 2011·Granted Dec 17, 2013·5 cites·22 claims
- 1161US9508615B2Clock tree synthesis for low cost pre-bond testing of 3D integrated circuitsQUALCOMM INC·Filed 2015·Granted Nov 29, 2016·1 cites·20 claims
- 1259US9537471B2Three dimensional logic circuitQUALCOMM INC·Filed 2015·Granted Jan 3, 2017·1 cites·18 claims
- 1351US2019027435A1Power distribution networks for a three-dimensional (3d) integrated circuit (ic) (3dic)QUALCOMM INC·Filed 2018·Application pending·0 cites
- 1448US9093995B2Length-of-diffusion protected circuit and method of designQUALCOMM INC·Filed 2013·Granted Jul 28, 2015·0 cites·21 claims
- 1546US2015112646A1METHODS OF DESIGNING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS AND COMPONENTSQUALCOMM INC·Filed 2013·Application pending·0 cites
- 1644US2015333005A1PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACQUALCOMM INC·Filed 2015·Application pending·0 cites
- 1743US9053960B2Decoupling capacitor for integrated circuitQUALCOMM INC·Filed 2013·Granted Jun 9, 2015·0 cites·8 claims
- 1840US9929733B1Connection propagation for inter-logical block connections in integrated circuitsQUALCOMM INC·Filed 2017·Granted Mar 27, 2018·0 cites·16 claims
- 1939US10062680B2Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methodsQUALCOMM INC·Filed 2014·Granted Aug 28, 2018·0 cites·9 claims
- 2037US2015019802A1Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioningQUALCOMM INC·Filed 2013·Application pending·0 cites
- 2135US2016042110A1High quality physical design for monolithic three-dimensional integrated circuits (3d ic) using two-dimensional integrated circuit (2d ic) design toolsQUALCOMM INC·Filed 2015·Application pending·0 cites
- 2233US2013032885A1Area efficient gridded polysilicon layoutsQUALCOMM INC·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →