Inventor
SINGH GURBIR
US44 patents
⚠️ This page may combine multiple inventors who share the name “SINGH GURBIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS6601121B2Jul 29, 2003
Quad pumped bus architecture and protocol
INTEL CORP104 citations99
US6006299ADec 21, 1999
Apparatus and method for caching lock conditions in a multi-processor system
INTEL CORP94 citations98
US5581782ADec 3, 1996
Computer system with distributed bus arbitration scheme for symmetric and priority agents
INTEL CORP117 citations98
US6118306ASep 12, 2000
Changing clock frequency
INTEL CORP164 citations97
USRE38388EJan 13, 2004
Method and apparatus for performing deferred transactions
INTEL CORP50 citations96
US6609171B1Aug 19, 2003
Quad pumped bus architecture and protocol
INTEL CORP34 citations96
US5809524ASep 15, 1998
Method and apparatus for cache memory replacement line identification
INTEL CORP57 citations96
US5796977AAug 18, 1998
Highly pipelined bus architecture
INTEL CORP89 citations96
US5754833AMay 19, 1998
Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio
INTEL CORP77 citations96
US5715428AFeb 3, 1998
Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system
INTEL CORP82 citations96
US5615343AMar 25, 1997
Method and apparatus for performing deferred transactions
INTEL CORP69 citations96
US5568620AOct 22, 1996
Method and apparatus for performing bus transactions in a computer system
INTEL CORP58 citations96
US6202125B1Mar 13, 2001
Processor-cache protocol using simple commands to implement a range of cache configurations
INTEL CORP83 citations94
US6907487B2Jun 14, 2005
Enhanced highly pipelined bus architecture
INTEL CORP22 citations93
US6880031B2Apr 12, 2005
Snoop phase in a highly pipelined bus architecture
INTEL CORP18 citations93
US6807592B2Oct 19, 2004
Quad pumped bus architecture and protocol
INTEL CORP16 citations93
US6804735B2Oct 12, 2004
Response and data phases in a highly pipelined bus architecture
INTEL CORP21 citations93
US5937171AAug 10, 1999
Method and apparatus for performing deferred transactions
INTEL CORP26 citations93
US5923857AJul 13, 1999
Method and apparatus for ordering writeback data transfers on a bus
INTEL CORP20 citations93
US5911053AJun 8, 1999
Method and apparatus for changing data transfer widths in a computer system
INTEL CORP34 citations93
US5903738AMay 11, 1999
Method and apparatus for performing bus transactions in a computer system
INTEL CORP24 citations93
US5903908AMay 11, 1999
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
INTEL CORP60 citations93
US5832534ANov 3, 1998
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories
INTEL CORP43 citations93
US5678020AOct 14, 1997
Memory subsystem wherein a single processor chip controls multiple cache memory chips
INTEL CORP36 citations93
US5701503ADec 23, 1997
Method and apparatus for transferring information between a processor and a memory system
INTEL CORP27 citations92
US6311281B1Oct 30, 2001
Apparatus and method for changing processor clock ratio settings
INTEL CORP28 citations91
US5345576ASep 6, 1994
Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
INTEL CORP54 citations91
US4803622AFeb 7, 1989
Programmable I/O sequencer for use in an I/O processor
INTEL CORP45 citations89
US6405271B1Jun 11, 2002
Data flow control mechanism for a bus supporting two-and three-agent transactions
INTEL CORP12 citations82
US5966722AOct 12, 1999
Method and apparatus for controlling multiple dice with a single die
INTEL CORP9 citations74
AGILENT TECHNOLOGIES INC
4 patentsUS6967321B2Nov 22, 2005
Optical navigation sensor with integrated lens
AGILENT TECHNOLOGIES INC75 citations96
US6879040B2Apr 12, 2005
Surface mountable electronic device
AGILENT TECHNOLOGIES INC20 citations93
US6242280B1Jun 5, 2001
Method of interconnecting an electronic device
AGILENT TECHNOLOGIES INC19 citations90
US6768101B1Jul 27, 2004
High resolution optical encoder with an angular collimated light beam
AGILENT TECHNOLOGIES INC18 citations89
CADENCE DESIGN SYSTEMS INC
3 patentsUS7836102B2Nov 16, 2010
Method and system for enhancing software documentation and help systems
CADENCE DESIGN SYSTEMS INC7 citations74
US7797353B1Sep 14, 2010
Method and system for enhancing software documentation and help systems
CADENCE DESIGN SYSTEMS INC5 citations74
US7937418B2May 3, 2011
Method and system for enhancing software documentation and help systems
CADENCE DESIGN SYSTEMS INC0 citations52