Method and apparatus for performing deferred transactions

Abstract

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

We claim:  
     
       1. A computer system comprising: 
       an address bus; and  
       a requesting agent coupled to the bus and operable to issue a request onto the bus in a first bus transaction by driving an address onto the address bus in a first clock cycle of the first bus transaction and request identification information consecutively onto the address bus in a second clock cycle of the first bus transaction , wherein said requesting agent comprises:  
       a pending defer queue to store pending requests,  
       a first logic circuit to recognize a subsequent deferred reply on the bus in a second bus transaction as corresponding to the request in the pending defer queue, wherein the requesting agent processes the deferred reply as a response to the request substantially as if undeterred  undeferred.  
     
     
       2. The computer system defined in  claim 1  wherein the pending defer queue comprises a plurality of entries, wherein each of the plurality of entries comprises a plurality of fields to store the request identification information, wherein one of the plurality of fields stores a token and another of the plurality of fields stores request information associated with the token. 
     
     
       3. The computer system defined in  claim 1  wherein the first logic circuit comprises: 
       a latch coupled to receive a token identifying the subsequent deferred reply on the bus;  
       matching logic coupled to the latch and configured to compare an identification (ID) of the requesting agent to a first portion of the token, wherein the requesting agent indexes the pending defer queue with a second portion of the token if the matching logic determines that the ID matches the first portion of the token.  
     
     
       4. A computer system comprising: 
       an address bus; and  
       a requesting agent coupled to the address bus and including,  
       means for issuing an address and a request identification token pairs  onto the address bus in consecutive bus cycles  consecutively for each bus request as art  part of a bus transaction.  
     
     
       5. The computer system of  claim 4  wherein the requesting agent further comprises: 
       means for responding to a deferred reply on the address bus as if not deferred.  
     
     
       6. A computer system comprising: 
       an address bus; and  
       a requesting agent coupled to the bus and operable to issue a request onto the address bus in a first bus transaction by driving an address and request identification information onto the address bus, wherein said requesting agent comprises:  
       a pending defer queue to store pending data requests,  
       a first logic circuit to recognize a subsequent deferred reply on the address bus in a second bus transaction as corresponding to the request in the pending defer queue, wherein the requesting agent processes the deferred reply as a response to the request substantially as if undeferred.  
     
     
       7. A method of performing bus operations in a computer system having an address bus and a data bus, the method comprising steps of: 
       a first agent sending an address on the address bus to a second agent;  
       sending a first token on the address bus to the second agent;  
       providing a first response to the first agent indicating that the second agent is to provide a deferred reply in response to the address;  
       sending a second token on the address bus to the first agent;  
       the second agent sending the deferred reply on the address bus to the first agent; and  
       recognizing the second token and deferred reply as corresponding to the address and the first token.  
     
     
       8. The method defined in  claim 7  wherein the first token is sent on the address bus in the clock cycle immediately after the address is sent on the address bus. 
     
     
       9. The method defined in  claim 7  further comprising the step of asserting at least one signal indicating the address bus contains token information when the second agent sends the second token on the address bus. 
     
     
       10. The method defined in  claim 7  wherein the first and second tokens are the same. 
     
     
       11. The method defined in  claim 7  further comprising the step of driving data onto the data bus when the second agent sends the deferred reply. 
     
     
       12. The method defined in  claim 7  wherein the step of recognizing comprises the step of matching the second token to the first token. 
     
     
       13. A computer system comprising: 
       an address bus;  
       a requesting agent coupled to the address bus and including,  
       a first logic circuit configured to issue an address and a request identification token pairs  onto the address bus in consecutive bus cycles  consecutively for each  a bus request as part of a bus transaction.  
     
     
       14. The computer system of  claim 13  wherein the requesting agent further comprises: 
       a second logic circuit configured to respond to a deferred reply on the address bus as if not deferred.  
     
     
       15. A method for performing bus operations in a computer system having an address bus and a data bus, the method comprising steps of: 
       a first agent initiating a bus request as part of a bus operation, wherein the step of initiating a bus request comprises driving an address on the address bus  
       a first agent driving a first token on the address bus;  
       providing a first response to the first agent indicating that a second agent is to provide a deferred reply in response to the address and the second agent receiving the first token from the address bus;  
       the second agent driving a second token on the address bus;  
       the second agent sending the deferred reply to the first agent;  
       the first agent receiving the second token from the address bus;  
       the first agent identifying the second token as corresponding to the bus operation; and  
       receiving the deferred reply by the first agent, thereby completing the bus operation.  
     
     
       16. The method defined in  claim 15  wherein the second token is the same as the first token, such that the first agent identifies the second token as corresponding to the bus operation by comparing the first token and the second token to determine if the first token and the second token are the same. 
     
     
       17. The method defined in  claim 15  wherein the step of driving the second token comprises asserting at least one signal indicating that the address bus contains token information. 
     
     
       18. The method defined in  claim 15  wherein the step of sending the deferred reply comprises sending at least one completion signal to the first agent. 
     
     
       19. The method defined in  claim 15  wherein the step of sending the deferred reply comprises driving data on the data bus. 
     
     
       20. A method for performing bus transactions in a computer system having an address bus and a data bus, the method comprising the steps of: 
       a first agent driving an address and a first token on the address bus as part of a request to initiate a first bus transaction;  
       latching the first token;  
       sending a deferral response in response to the request;  
       the first agent receiving the deferral response to complete the first bus transaction;  
       a second agent sending a deferred reply as part of a second bus transaction, wherein the step of sending a deferred reply comprises sending a second token on the address bus; and  
       the first agent identifying the defined reply corresponding to the request, such that the request is completed using two bus transactions.  
     
     
       21. The method defined in  claim 20  wherein the step of identifying includes comparing the first token and the second token and receiving the deferred reply if the first token and the second match. 
     
     
       22. The method defined in  claim 20  further comprising the step of buffering the address and the first token for use as a reference when receiving the deferred reply. 
     
     
       23. A computer system comprising: 
       an address bus;  
       a data bus;  
       a control bus;  
       a first bus agent coupled to the address bus, the data bus, and the control bus for performing a bus operation wherein the first bus agent initiates the bus operation by initiating a first bus transaction by driving a request address of a request and request identification information onto the address bus during consecutive clock cycles  consecutively, and terminates the first bus transaction upon receiving an immediate response to satisfy the request or a deferral response indication on the control bus indicating response to the request is to be deferred.  
     
     
       24. The computer system defined in  claim 23  further comprising a second bus agent for providing the immediate response to the first bus agent. 
     
     
       25. The computer system defined in  claim 23  further comprising a second bus agent for providing the deferral response to the first bus agent. 
     
     
       26. The computer system defined in  claim 23  further comprising a second bus agent to initiate a second bus transaction, in response to the first bus transaction, by driving the request identification information and a deferral reply onto the address bus. 
     
     
       27. The computer system deferred in  claim 26  wherein the first bus agent receives the request identification information and deferred reply and associates the deferred reply with the request of the first bus transaction to complete the bus operation. 
     
     
       28. A method of performing bus transactions in a computer system having a requesting agent and a responding agent each coupled to a bus which includes a response bus, an address bus, and a data bus, the method comprising the steps of: 
       the requesting agent requesting a first bus transaction by issuing an address and a token onto the address bus; and  
       if the responding agent is ready to perform the first bus transaction, the responding agent driving an in-order completion response onto the response bus in a response phase of the first bus transaction; and  
       if the responding agent is not ready to perform the first bus transaction, then  
       the responding agent driving a deferral response onto the response bus in the response phase of the first bus transaction, and when the responding agent becomes ready to respond, then the responding agent initiating a second bus transaction and driving a deferred reply onto the address bus, a second token onto the address bus, and any requested data onto the data bus, in response phase of the second bus transaction.  
     
     
       29. A computer system comprising: 
       a bus including:  
       an address bus;  
       a response bus;  
       a data bus;  
       a requesting agent coupled to the bus, wherein the requesting agent issues a token onto the address bus for each address request and handles deferral responses in response to requests, and maintains the request as pending until receiving a deferred reply; and  
       a responding agent coupled to the bus, wherein the responding agent generates the deferral response when a transaction cannot be completed during a predetermined time, and the responding agent generates the deferred reply, including the token, when the transaction can be completed.  
     
     
       30. A method of performing bus operations in a computer system having an address bus and a data bus, the method comprising: 
       a first agent sending an address on the address bus to a second agent;  
       sending a first token on the address bus to the second agent;  
       the first agent receiving a first response from the second agent indicating that the second agent is to provide a deferred reply in response to the address;  
       the first agent receiving a second token driven on the address bus by the second agent;  
       the first agent receiving the deferred reply driven on the address bus by the second agent; and  
       recognizing the second token and deferred reply as corresponding to the address and the first token.  
     
     
       31. The method defined in  claim 30  wherein the first token is sent on the address bus in the clock cycle immediately after the address is sent on the address bus. 
     
     
       32. The method defined in  claim 30  further comprising asserting at least one signal indicating the address bus contains token information when the second agent sends the second token on the address bus. 
     
     
       33. The method defined in  claim 30  wherein the first and second tokens are the same. 
     
     
       34. The method defined in  claim 30  further comprising receiving data driven onto the data bus by the second agent with the deferred reply. 
     
     
       35. The method defined in  claim 30  wherein recognizing the second token comprises matching the second token to the first token. 
     
     
       36. A method for performing bus transactions in a computer system having an address bus and a data bus, the method comprising: 
       a first agent driving an address and a first token on the address bus as part of a request to initiate a first bus transaction;  
       the first agent receiving a deferral response from a second agent to complete the first bus transaction;  
       the first agent receiving a deferred reply as part of a second bus transaction, wherein receiving the deferred reply comprises receiving a second token on the address bus; and  
       the first agent identifying the deferred reply as corresponding to the request, such that the request is completed using two bus transactions.  
     
     
       37. The method defined in  claim 36  wherein identifying the deferred reply includes comparing the first token and the second token and receiving the deferred reply if the first token and the second match. 
     
     
       38. The method defined in  claim 36  further comprising buffering the address and the first token for use as a reference when receiving the deferred reply. 
     
     
       39. A method for performing bus operations in a computer system having an address bus and a data bus, the method comprising: 
       a first agent receiving an address on the address bus for a bus request as part of a bus operation from a second agent;  
       providing a first response to the second agent indicating that the first agent is to provide a deferred reply in response to the address and the first agent receiving a first token from the address bus;  
       the first agent driving a second token on the address bus; and  
       the first agent sending the deferred reply to the second agent to complete the bus operation once the second agent receives and the second token from the address bus and identifies the second token as corresponding to the bus operation.  
     
     
       40. The method defined in  claim 39  wherein the second token is the same as the first token, such that the second agent identifies the second token as corresponding to the bus operation by comparing the first token and the second token to determine if the first token and the second token are the same. 
     
     
       41. The method defined in  claim 39  wherein driving the second token comprises asserting at least one signal indicating that the address bus contains token information. 
     
     
       42. The method defined in  claim 39  wherein sending the deferred reply comprises sending at least one completion signal to the first agent. 
     
     
       43. The method defined in  claim 39  wherein sending the deferred reply comprises driving data on the data bus. 
     
     
       44. A bus agent comprising: 
       
         bus interface logic to issue a request in a first bus transaction by driving an address and request identification information consecutively to an address bus interface, the bus interface logic comprising:  
       
       
         a pending defer queue to store pending requests;  
       
       
         a first logic circuit to recognize a subsequent deferred reply in a second bus transaction as corresponding to the request in the pending defer queue, wherein the bus agent processes the deferred reply as a response to the request substantially as if undeferred. 
       
     
     
       45. The bus agent defined in  claim 44  wherein the pending defer queue comprises a plurality of entries, wherein each of the plurality of entries comprises a plurality of fields to store the request identification information, wherein one of the plurality of fields stores a token and another of the plurality of fields stores request information associated with the token. 
     
     
       46. The bus agent defined in  claim 44  wherein the first logic circuit comprises: 
       
         a latch coupled to receive a token identifying the subsequent deferred reply on the address bus interface;  
       
         matching logic coupled to the latch to compare an identification  ( ID )  of the bus agent to a first portion of the token, wherein the bus agent is to index the pending defer queue with a second portion of the token if the matching logic determines that the ID matches the first portion of the token.   
     
     
       47. An apparatus comprising: 
       
         an address bus interface; and  
       
       
         means for issuing an address and a request identification token to the address bus interface consecutively for each bus request as part of a request phase of a bus transaction. 
       
     
     
       48. The apparatus of  claim 47  further comprising: 
       
         means for responding to a deferred reply on the address bus interface as if not deferred. 
       
     
     
       49. A bus agent comprising: 
       
         an address bus interface; and  
       
       
         logic coupled to the address bus interface to issue a request to the address bus interface in a first bus transaction by driving an address and request identification information to the address bus interface, wherein said logic comprises:  
       
       
         a pending defer queue to store pending data requests,  
       
       
         a first logic circuit to recognize a subsequent deferred reply received at the address bus interface in a second bus transaction as corresponding to the request in the pending defer queue, wherein the bus agent processes the deferred reply as a response to the request substantially as if undeferred. 
       
     
     
       50. A bus agent comprising: 
       
         an address bus interface;  
       
       
         a first logic circuit to issue an address and a request identification token to the address bus interface consecutively for a bus request as part of a bus transaction. 
       
     
     
       51. The bus agent of  claim 50  wherein the bus agent further comprises: 
       
         a second logic circuit configured to respond to a deferred reply on the address bus interface as if not deferred. 
       
     
     
       52. A bus agent comprising: 
       
         an address bus interface;  
       
       
         a data bus interface;  
       
       
         a control bus interface;  
       
       
         logic coupled to the address bus interface, the data bus interface, and the control bus interface to perform a bus operation wherein the bus agent is to initiate the bus operation by initiating a first bus transaction by driving a request address of a request and request identification information to the address bus interface consecutively, and is to terminate the first bus transaction upon receiving a response to satisfy the request or a deferral response indication on the control bus interface indicating response to the request is to be deferred. 
       
     
     
       53. The bus agent of  claim 52  wherein the bus agent receives the request identification information and a deferred reply and associates the deferred reply with the request of the first bus transaction to complete the bus operation. 
     
     
       54. A bus agent comprising: 
       
         an address bus interface;  
       
       
         a data bus interface;  
       
       
         a control bus interface;  
       
       
         logic coupled to the address bus interface, the data bus interface, and the control bus interface to perform a bus operation wherein the bus agent is to initiate the bus operation by initiating a first bus transaction by driving a request address of a request to the address bus interface and request identification information during a first phase of the first bus transaction, and is to terminate the first bus transaction upon receiving a response to satisfy the request or a deferral response indication on the control bus interface indicating response to the request is to be deferred. 
       
     
     
       55. The bus agent of  claim 54  wherein the bus agent is to receive a deferred reply including the request identification information and to associate the deferred reply with the request of the first bus transaction to complete the bus operation. 
     
     
       56. The bus agent defined in  claim 55  wherein the bus agent is to associate the deferred reply with the request using the request identification information. 
     
     
       57. The bus agent defined in  claim 54  wherein the first phase is a request phase and wherein said deferral response indication comprises an asserted defer signal in a snoop phase and a defer response in a response phase. 
     
     
       58. The bus agent defined in  claim 54  wherein the request identification information comprises a token. 
     
     
       59. A bus agent comprising: 
       
         an address bus interface to receive a first token associated with a request phase of a first bus transaction that is a request; and  
       
       
         bus interface logic to provide a response indicating that a deferred reply is to be made by said bus agent to satisfy said request in response to said bus agent not being ready to complete the request, to allow the first bus transaction to complete, wherein said bus agent is to drive a second token via the address bus interface and the deferred reply as a second bus transaction when ready, the second token corresponding to the request, the deferred reply returning information requested in the request. 
       
     
     
       60. The bus agent of  claim 59  wherein said bus interface logic is only to provide the response indicating that the deferred reply is to be made if said bus interface logic receives a defer enable signal. 
     
     
       61. The bus agent of  claim 60  wherein said bus agent further comprises: 
       
         an arbitration signal interface;  
       
       
         a snoop signal interface;  
       
       
         a data bus interface, wherein said bus agent is to support a pipelined bus protocol, allowing different phases of different transactions to be active during a single bus clock cycle. 
       
     
     
       62. The bus agent of  claim 61  wherein said bus agent supports overlapping request and arbitration phases and overlapping request and snoop phases. 
     
     
       63. The bus agent of  claim 61  wherein said defer enable signal is received as a part of the request phase and further wherein said response indicating that the deferred reply is to be made by said bus agent comprises a defer signal asserted in a snoop phase and a response asserted in a response phase. 
     
     
       64. A system comprising: 
       
         a data bus;  
       
       
         an address bus;  
       
       
         a snoop bus;  
       
       
         an arbitration bus;  
       
       
         a requesting bus agent coupled to said data bus, said address bus, said snoop bus, and said arbitration bus, said requesting bus agent to support a pipelined bus protocol in which multiple different transaction phases of different transactions are in some cases active on different buses during a single clock cycle, wherein the requesting bus agent is to signal a request and a request token consecutively on said address bus in a request phase of a first transaction;  
       
       
         a responding bus agent coupled to said data bus, said address bus, said snoop bus, and said arbitration bus, said responding bus agent to provide a defer indication to said requesting bus agent to end said first transaction. 
       
     
     
       65. The system of  claim 64  further comprising: 
       
         a defer enable signal line, wherein said requesting bus agent is to generate an active defer enable signal on said defer enable signal line during the request phase of said first transaction;  
       
       
         a defer signal line, wherein said responding bus agent is to generate an active defer signal on said defer signal line during a snoop phase of said first transaction to provide a first portion of said defer indication;  
       
       
         a plurality of response signal lines, wherein said responding bus agent is to generate a defer response encoding on said plurality of response signal lines during a response phase to provide a second portion of said defer indication. 
       
     
     
       66. A bus agent comprising: 
       
         a data bus interface;  
       
       
         an address bus interface;  
       
       
         a snoop interface;  
       
       
         an arbitration interface;  
       
       
         bus control logic coupled to said data bus interface, said address bus interface, said snoop interface, and said arbitration interface, to support a pipelined bus protocol in which multiple different transaction phases of different transactions are in some cases active on different buses during a single clock cycle, wherein the bus control logic is to signal a request and a request token consecutively on said address bus interface in a request phase of a first transaction. 
       
     
     
       67. The bus agent of  claim 66  further comprising: 
       
         a defer enable interface, wherein said bus control logic is to generate an active defer enable signal on said defer enable interface during the request phase of said first transaction, and further wherein said bus control logic is to end said first transaction in response to a defer signal in a snoop phase and a deferral encoding on a response bus in a response phase. 
       
     
     
       68. A bus agent comprising: 
       
         a data bus interface;  
       
       
         an address bus interface;  
       
       
         a snoop interface;  
       
       
         an arbitration interface;  
       
       
         bus control logic coupled to said data bus interface, said address bus interface, said snoop interface, and said arbitration interface, to support a pipelined bus protocol in which multiple different transaction phases of different transactions are in some cases active on different buses during a single clock cycle, to provide a defer indication to end a first transaction in response to a consecutively received address and a token received on said address bus interface during a request phase of the first transaction, said bus control logic to initiate a second transaction in which said token is driven on said address bus interface during a second transaction request phase and wherein information requested in the first transaction is provided during a data phase of the second transaction. 
       
     
     
       69. The bus agent of  claim 68  further comprising: 
       
         a defer enable interface, wherein said bus control logic is only to provide the defer indication if an active defer enable signal is received on the defer enable interface during the request phase of said first transaction; and  
       
       
         a defer signal interface, wherein said bus control logic is to generate an active defer signal on said defer signal interface during a snoop phase of said first transaction to provide a first portion of said defer indication;  
       
       
         a response interface, wherein said bus control logic is to generate a defer response encoding on said response interface during a response phase to provide a second portion of said defer indication only if no hit modified signal is received on said snoop interface during said snoop phase. 
       
     
     
       70. The apparatus of  claim 47  further comprising: 
       
         a data bus interface;  
       
       
         a snoop interface;  
       
       
         means for participating in different transaction phases for different transactions on two of said data bus interface, said address bus interface, and said snoop interface. 
       
     
     
       71. The apparatus of  claim 70  further comprising: 
       
         a defer enable signal interface;  
       
       
         means for asserting an active defer enable signal during the request phase of the bus transaction to allow said bus transaction to be deferred;  
       
       
         a defer signal interface;  
       
       
         means to receive an active defer signal on said defer signal interface during a snoop phase of the bus transaction and a deferral response during a response phase of the bus transaction and to conclude said bus transaction in response to said active defer signal and said deferral response. 
       
     
     
       72. The bus agent of  claim 50  further comprising: 
       
         a defer enable signal interface;  
       
       
         a defer signal interface;  
       
       
         a response interface;  
       
       
         a second logic circuit to assert an active defer enable signal during a request phase of the bus transaction to allow said bus transaction to be deferred and to receive an active defer signal from said defer signal interface during a snoop phase of the bus transaction and a deferral response encoding on said response interface in a response phase and to conclude said bus transaction in response to said active defer signal and said deferral response encoding. 
       
     
     
       73. The bus agent of  claim 72  wherein said bus agent further comprises a data bus interface, and a snoop interface, and wherein said bus agent is to participate in different transaction phases for different transactions on two of said data bus interface, said address bus interface, said response interface, and said snoop interface.