Inventor · disambiguated record
Stephen S. Pawlowski
Also filed as: PAWLOWSKI STEPHEN · PAWLOWSKI STEPHEN S · PAWLOWSKI STEPHEN SCOTT
67 granted patents·9 pending applications·1,872 citations·filing 1989–2025
99Inventor score
Top patents by PatentIndex Score
76 records- 0197US11404136B2Memory device protection using interleaved multibit symbolsMICRON TECHNOLOGY INC·Filed 2020·Granted Aug 2, 2022·6 cites·22 claims
- 0297US6601121B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Jul 29, 2003·104 cites·23 claims
- 0391USRE38388EMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 2001·Granted Jan 13, 2004·50 cites·73 claims
- 0490US5905876AQueue ordering for memory and I/O transactions in a multiple concurrent transaction computer systemINTEL CORP·Filed 1996·Granted May 18, 1999·163 cites·15 claims
- 0583US6907487B2Enhanced highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Jun 14, 2005·22 cites·62 claims
- 0683US6195712B1Dynamic discovery of wireless peripheralsINTEL CORP·Filed 1997·Granted Feb 27, 2001·129 cites·10 claims
- 0783US5615343AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1994·Granted Mar 25, 1997·69 cites·31 claims
- 0882US6804735B2Response and data phases in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Oct 12, 2004·21 cites·21 claims
- 0980US5796977AHighly pipelined bus architectureINTEL CORP·Filed 1996·Granted Aug 18, 1998·89 cites·16 claims
- 1079US6880031B2Snoop phase in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Apr 12, 2005·18 cites·22 claims
- 1178US6807592B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Oct 19, 2004·16 cites·25 claims
- 1277US2025298749A1Memory controller architectureMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 1375US2024427526A1Memory controller for managing raid informationMICRON TECHNOLOGY INC·Filed 2024·Application pending·0 cites
- 1473US12332803B2Memory controller architectureMICRON TECHNOLOGY INC·Filed 2023·Granted Jun 17, 2025·0 cites·16 claims
- 1572US5906001AMethod and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routinesINTEL CORP·Filed 1996·Granted May 18, 1999·61 cites·16 claims
- 1671US5978737AMethod and apparatus for hazard detection and distraction avoidance for a vehicleINTEL CORP·Filed 1997·Granted Nov 2, 1999·63 cites·21 claims
- 1770US11461011B2Extended line width memory-side cache systems and methodsMICRON TECHNOLOGY INC·Filed 2020·Granted Oct 4, 2022·0 cites·20 claims
- 1870US5696910AMethod and apparatus for tracking transactions in a pipelined busINTEL CORP·Filed 1995·Granted Dec 9, 1997·57 cites·22 claims
- 1969US11942175B2Memory device protection using interleaved multibit symbolsMICRON TECHNOLOGY INC·Filed 2022·Granted Mar 26, 2024·0 cites·19 claims
- 2069US10831377B2Extended line width memory-side cache systems and methodsMICRON TECHNOLOGY INC·Filed 2020·Granted Nov 10, 2020·0 cites·20 claims
- 2169US6609171B1Quad pumped bus architecture and protocolINTEL CORP·Filed 1999·Granted Aug 19, 2003·34 cites·64 claims
- 2269US6594756B1Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processorINTEL CORP·Filed 1999·Granted Jul 15, 2003·52 cites·22 claims
- 2369US6263397B1Mechanism for delivering interrupt messagesINTEL CORP·Filed 1998·Granted Jul 17, 2001·51 cites·36 claims
- 2467US12093566B2Memory controller for managing raid informationMICRON TECHNOLOGY INC·Filed 2022·Granted Sep 17, 2024·0 cites·20 claims
- 2567US5903916AComputer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operationINTEL CORP·Filed 1996·Granted May 11, 1999·50 cites·15 claims
- 2667US5548734AEqual length symmetric computer bus topologyINTEL CORP·Filed 1995·Granted Aug 20, 1996·34 cites·20 claims
- 2766US6219741B1Transactions supporting interrupt destination redirection and level triggered interrupt semanticsINTEL CORP·Filed 1997·Granted Apr 17, 2001·52 cites·10 claims
- 2865US6381665B2Mechanisms for converting interrupt request signals on address and data lines to interrupt message signalsINTEL CORP·Filed 2000·Granted Apr 30, 2002·8 cites·21 claims
- 2965US6151663ACluster controller for memory and data cache in a multiple cluster processing systemINTEL CORP·Filed 1998·Granted Nov 21, 2000·42 cites·5 claims
- 3065US5919254AMethod and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing systemINTEL CORP·Filed 1997·Granted Jul 6, 1999·47 cites·18 claims
- 3164US12282433B2Cache bypassMICRON TECHNOLOGY INC·Filed 2023·Granted Apr 22, 2025·0 cites·17 claims
- 3264US6418496B2System and apparatus including lowest priority logic to select a processor to receive an interrupt messageINTEL CORP·Filed 1997·Granted Jul 9, 2002·45 cites·24 claims
- 3363US11086526B2Adaptive line width cache systems and methodsMICRON TECHNOLOGY INC·Filed 2018·Granted Aug 10, 2021·0 cites·23 claims
- 3463US10691347B2Extended line width memory-side cache systems and methodsMICRON TECHNOLOGY INC·Filed 2018·Granted Jun 23, 2020·0 cites·17 claims
- 3561US10146657B2Initialization trace of a computing deviceSWANSON ROBERT C·Filed 2014·Granted Dec 4, 2018·1 cites·25 claims
- 3661US5961621AMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 1997·Granted Oct 5, 1999·32 cites·9 claims
- 3760US9547615B2Peripheral protocol negotiationBELL DENNIS M·Filed 2011·Granted Jan 17, 2017·2 cites·27 claims
- 3860US5537640AAsynchronous modular bus architecture with cache consistencyINTEL CORP·Filed 1994·Granted Jul 16, 1996·35 cites·11 claims
- 3960US2025245164A1Cache bypassMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 4059US2025335357A1Fixed ratio memory tiering with variable cache line sizeMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 4158US6012118AMethod and apparatus for performing bus operations in a computer system using deferred replies returned without using the address busINTEL CORP·Filed 1997·Granted Jan 4, 2000·34 cites·39 claims
- 4258US5956516AMechanisms for converting interrupt request signals on address and data lines to interrupt message signalsINTEL CORP·Filed 1997·Granted Sep 21, 1999·25 cites·16 claims
- 4358US5911053AMethod and apparatus for changing data transfer widths in a computer systemINTEL CORP·Filed 1996·Granted Jun 8, 1999·34 cites·14 claims
- 4458US5848279AMechanism for delivering interrupt messagesINTEL CORP·Filed 1996·Granted Dec 8, 1998·30 cites·6 claims
- 4557US6412060B2Method and apparatus for supporting multiple overlapping address spaces on a shared busINTEL CORP·Filed 2001·Granted Jun 25, 2002·4 cites·19 claims
- 4656US5513331AMethod and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system resetINTEL CORP·Filed 1995·Granted Apr 30, 1996·32 cites·4 claims
- 4756US2025245098A1Error management of memory devicesMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 4854US6108735AMethod and apparatus for responding to unclaimed bus transactionsINTEL CORP·Filed 1995·Granted Aug 22, 2000·29 cites·12 claims
- 4953US7831819B2Filter micro-coded acceleratorINTEL CORP·Filed 2004·Granted Nov 9, 2010·4 cites·22 claims
- 5053US6415367B1Apparatus for reducing asynchronous service latency in a time slot-based memory arbitration schemeINTEL CORP·Filed 1999·Granted Jul 2, 2002·25 cites·28 claims
Showing the top 50 of 76 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →