Mechanisms for converting interrupt request signals on address and data lines to interrupt message signals

Abstract

In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals. A redirection table includes a send pending bit to be set in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal.

What is claimed is:  
     
       1. An apparatus, comprising: 
       ports to receive an interrupt request signal in the form of address signals and data signals;  
       decode logic to receive at least some of the address signals and data signals and to provide a decoded signal at one of several decode output lines of the decode logic;  
       a redirection table including a send pending bit that is set responsive to the decode signal; and  
       encode/decode logic coupled between the redirection table and a bus and to communicate an interrupt message responsive to the send pending bit.  
     
     
       2. The apparatus of  claim 1 , further including a holding register that is set in response to assertion of the decoding signal. 
     
     
       3. The apparatus of  claim 1 , wherein the interrupt request signal is in the form of the address signals, the data signals, and other signals. 
     
     
       4. The apparatus of  claim 1 , wherein the apparatus is a bridge. 
     
     
       5. An apparatus, comprising: 
       dedicated interrupt ports to receive an interrupt request signal;  
       additional ports capable of receiving an interrupt request signal in the form of address signals and data signals;  
       decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals;  
       a redirection table including a send pending bit to be set in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal; and  
       processing circuitry; and  
       encode/decode logic coupled between the processing circuitry and the additional ports.  
     
     
       6. The apparatus of  claim 5 , wherein OR gates are positioned between the interrupt ports, some of the decode lines, and the redirection table. 
     
     
       7. An apparatus, comprising: 
       dedicated interrupt ports to receive an interrupt request signal from interrupt request lines;  
       ports to receive address and data signals;  
       decode logic to receive at least some of the address and data signals and to decode an interrupt request signal from them;  
       redirection and control circuitry coupled to the dedicated interrupt request ports and the decode logic to receive the interrupt request signal from the interrupt ports and the interrupt request signal from the decode logic and in response thereto to provide an interrupt message; and  
       encode/decode logic coupled between redirection and control circuitry and a bus and to communicate the interrupt message to the bus responsive to the redirection and control logic.  
     
     
       8. The apparatus of  claim 7 , wherein the interrupt request signal provided by the decode logic is identical to the interrupt request signal provided by the dedicated interrupt ports. 
     
     
       9. The apparatus of  claim 7 , wherein the redirection and control circuitry includes a redirection table. 
     
     
       10. The apparatus of  claim 1 , wherein the decode logic is included in an interrupt controller. 
     
     
       11. An apparatus, comprising: 
       dedicated interrupt ports to receive an interrupt request signal from interrupt request lines;  
       additional ports to receive address and data signals;  
       decode logic to receive at least some of the address and data signals and to decode an interrupt request signal from them;  
       a redirection table coupled to the dedicated interrupt request ports and the decode logic to receive the interrupt request signal from the interrupt ports and the interrupt request signal from the decode logic and in response thereto to provide an interrupt message; and  
       encode/decode logic coupled between the processing circuitry and the additional ports.  
     
     
       12. The apparatus of  claim 11 , wherein the interrupt request signal provided by the decode logic is identical to the interrupt request signal provided by the dedicated interrupt ports receiving the address and data signals. 
     
     
       13. The apparatus of  claim 11 , wherein the decode logic is included in an interrupt controller. 
     
     
       14. A computer system, comprising: 
       a processor;  
       an I/O bus;  
       peripheral devices connected to the I/O bus; and  
       a bridge including:  
       ports to receive address and data signals;  
       decode logic to receive at least some of the address and data signals and to decode an interrupt request signal from them; and  
       redirection and control circuitry coupled to the decode logic to receive the interrupt request signal the decode logic and in response thereto to provide an interrupt message; and  
       encode/decode logic coupled between the redirection and control circuitry and a bus and to communicate the interrupt message to the bus responsive the redirection and control circuitry.  
     
     
       15. The system of  claim 14 , wherein at least one of the peripheral devices can provide address and data signals to the decode logic for decoding an interrupt request signal from them. 
     
     
       16. An apparatus, comprising: 
       ports to receive an interrupt request signal in the form of address signals and data signals;  
       decode logic to receive at least some of the address signals and data signals and to provide a decoded signal at one of several decode output lines of the decode logic;  
       a redirection table to provide a send pending signal responsive to the decode signal; and  
       encode/decode logic coupled between the redirection table and a bus and to communicate an interrupt message responsive to the send pending signal.  
     
     
       17. The apparatus of  claim 16 , further including a holding register that is set in response to assertion of the decoding signal. 
     
     
       18. The apparatus of  claim 16 , wherein the interrupt request signal is in the form of the address signals, the data signals, and other signals. 
     
     
       19. The apparatus of  claim 16 , wherein the send pending signal is created through the setting of a send pending bit. 
     
     
       20. An apparatus, comprising: 
       dedicated interrupt ports to receive an interrupt request signal;  
       additional ports capable of receiving an interrupt request signal in the form of address signals and data signals;  
       decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals;  
       a redirection table to provide a send pending signal in response to either the interrupt request signal at the dedicated interrupt ports or in response to the decode signal; and  
       processing circuitry; and  
       encode/decode logic coupled between the processing circuitry and the additional ports.  
     
     
       21. The apparatus of  claim 20 , wherein OR gates are positioned between the interrupt ports, some of the decode lines, and the redirection table.