Inventor · disambiguated record
Peter D. Macwilliams
Also filed as: MACWILLIAMS PETER · MACWILLIAMS PETER D
61 granted patents·2 pending applications·3,199 citations·filing 1988–2012
99Inventor score
Top patents by PatentIndex Score
63 records- 0199US6477614B1Method for implementing multiple memory buses on a memory moduleINTEL CORP·Filed 2000·Granted Nov 5, 2002·308 cites·22 claims
- 0298US6587912B2Method and apparatus for implementing multiple memory buses on a memory moduleINTEL CORP·Filed 1998·Granted Jul 1, 2003·407 cites·32 claims
- 0396US6075730AHigh performance cost optimized memory with delayed memory writesRAMBUS INC·Filed 1998·Granted Jun 13, 2000·182 cites·6 claims
- 0495US8310854B2Identifying and accessing individual memory devices in a memory channelMACWILLIAMS PETER·Filed 2011·Granted Nov 13, 2012·21 cites·33 claims
- 0591US7872892B2Identifying and accessing individual memory devices in a memory channelINTEL CORP·Filed 2005·Granted Jan 18, 2011·21 cites·15 claims
- 0691USRE38388EMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 2001·Granted Jan 13, 2004·50 cites·73 claims
- 0790US5905876AQueue ordering for memory and I/O transactions in a multiple concurrent transaction computer systemINTEL CORP·Filed 1996·Granted May 18, 1999·163 cites·15 claims
- 0890US5355467ASecond level cache controller unit and systemINTEL CORP·Filed 1994·Granted Oct 11, 1994·211 cites·9 claims
- 0988US5822767AMethod and apparartus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Oct 13, 1998·109 cites·11 claims
- 1087US8866830B2Memory controller interface for micro-tiled memory accessMACWILLIAMS PETER·Filed 2012·Granted Oct 21, 2014·9 cites·15 claims
- 1186US5228134ACache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory busINTEL CORP·Filed 1991·Granted Jul 13, 1993·121 cites·27 claims
- 1284US8200883B2Micro-tile memory interfacesMACWILLIAMS PETER·Filed 2011·Granted Jun 12, 2012·8 cites·17 claims
- 1384US8064237B2Identifying and accessing individual memory devices in a memory channelMACWILLIAMS PETER·Filed 2010·Granted Nov 22, 2011·7 cites·26 claims
- 1483US8032688B2Micro-tile memory interfacesINTEL CORP·Filed 2005·Granted Oct 4, 2011·11 cites·14 claims
- 1583US6112016AMethod and apparatus for sharing a signal line between agentsINTEL CORP·Filed 1997·Granted Aug 29, 2000·83 cites·16 claims
- 1683US5615343AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1994·Granted Mar 25, 1997·69 cites·31 claims
- 1783US4785396APush-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuitINTEL CORP·Filed 1988·Granted Nov 15, 1988·91 cites·5 claims
- 1880US8253751B2Memory controller interface for micro-tiled memory accessMACWILLIAMS PETER·Filed 2005·Granted Aug 28, 2012·9 cites·4 claims
- 1980US5796977AHighly pipelined bus architectureINTEL CORP·Filed 1996·Granted Aug 18, 1998·89 cites·16 claims
- 2079US5293603ACache subsystem for microprocessor based computer system with synchronous and asynchronous data pathINTEL CORP·Filed 1991·Granted Mar 8, 1994·84 cites·18 claims
- 2177US5421734AMethod and apparatus for evolving bus from five volt to three point three volt operationINTEL CORP·Filed 1993·Granted Jun 6, 1995·41 cites·11 claims
- 2276US6226757B1Apparatus and method for bus timing compensationRAMBUS INC·Filed 1998·Granted May 1, 2001·76 cites·5 claims
- 2376US6202125B1Processor-cache protocol using simple commands to implement a range of cache configurationsINTEL CORP·Filed 1997·Granted Mar 13, 2001·83 cites·36 claims
- 2473US6442632B1System resource arbitration mechanism for a host bridgeINTEL CORP·Filed 2000·Granted Aug 27, 2002·18 cites·7 claims
- 2572US6633947B1Memory expansion channel for propagation of control and request packetsINTEL CORP·Filed 1998·Granted Oct 14, 2003·63 cites·37 claims
- 2672US5906001AMethod and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routinesINTEL CORP·Filed 1996·Granted May 18, 1999·61 cites·16 claims
- 2771US5572703AMethod and apparatus for snoop stretching using signals that convey snoop resultsINTEL CORP·Filed 1994·Granted Nov 5, 1996·47 cites·40 claims
- 2868US5651137AScalable cache attributes for an input/output busINTEL CORP·Filed 1995·Granted Jul 22, 1997·42 cites·24 claims
- 2968US5625779AArbitration signaling mechanism to prevent deadlock guarantee access latency, and guarantee acquisition latency for an expansion bridgeINTEL CORP·Filed 1994·Granted Apr 29, 1997·49 cites·8 claims
- 3067US5903916AComputer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operationINTEL CORP·Filed 1996·Granted May 11, 1999·50 cites·15 claims
- 3165US5919254AMethod and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing systemINTEL CORP·Filed 1997·Granted Jul 6, 1999·47 cites·18 claims
- 3263US6598103B2Transmission of signals synchronous to a common clock and transmission of data synchronous to strobes in a multiple agent processing systemINTEL CORP·Filed 2001·Granted Jul 22, 2003·8 cites·132 claims
- 3361US5961621AMechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined systemINTEL CORP·Filed 1997·Granted Oct 5, 1999·32 cites·9 claims
- 3460US5937171AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1996·Granted Aug 10, 1999·26 cites·43 claims
- 3560US5537640AAsynchronous modular bus architecture with cache consistencyINTEL CORP·Filed 1994·Granted Jul 16, 1996·35 cites·11 claims
- 3659US6247136B1Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environmentINTEL CORP·Filed 1998·Granted Jun 12, 2001·30 cites·26 claims
- 3758US6212589B1System resource arbitration mechanism for a host bridgeINTEL CORP·Filed 1997·Granted Apr 3, 2001·33 cites·21 claims
- 3858US6012118AMethod and apparatus for performing bus operations in a computer system using deferred replies returned without using the address busINTEL CORP·Filed 1997·Granted Jan 4, 2000·34 cites·39 claims
- 3958US5911053AMethod and apparatus for changing data transfer widths in a computer systemINTEL CORP·Filed 1996·Granted Jun 8, 1999·34 cites·14 claims
- 4057US6412060B2Method and apparatus for supporting multiple overlapping address spaces on a shared busINTEL CORP·Filed 2001·Granted Jun 25, 2002·4 cites·19 claims
- 4157US5948094AMethod and apparatus for executing multiple transactions within a single arbitration cycleINTEL CORP·Filed 1997·Granted Sep 7, 1999·32 cites·25 claims
- 4256US6336159B1Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing systemINTEL CORP·Filed 1998·Granted Jan 1, 2002·27 cites·191 claims
- 4356US6209072B1Source synchronous interface between master and slave using a deskew latchINTEL CORP·Filed 1997·Granted Mar 27, 2001·27 cites·11 claims
- 4456US5513331AMethod and apparatus for automatically configuring system memory address space of a computer system having a memory subsystem with indeterministic number of memory units of indeterministic sizes during system resetINTEL CORP·Filed 1995·Granted Apr 30, 1996·32 cites·4 claims
- 4552US5301299AOptimized write protocol for memory accesses utilizing row and column strobesINTEL CORP·Filed 1993·Granted Apr 5, 1994·23 cites·10 claims
- 4649US6128748AIndependent timing compensation of write data path and read data path on a common data busINTEL CORP·Filed 1998·Granted Oct 3, 2000·21 cites·33 claims
- 4748US5923857AMethod and apparatus for ordering writeback data transfers on a busINTEL CORP·Filed 1996·Granted Jul 13, 1999·20 cites·15 claims
- 4847US5996042AScalable, high bandwidth multicard memory system utilizing a single memory controllerINTEL CORP·Filed 1996·Granted Nov 30, 1999·19 cites·11 claims
- 4946US6405271B1Data flow control mechanism for a bus supporting two-and three-agent transactionsINTEL CORP·Filed 1996·Granted Jun 11, 2002·12 cites·15 claims
- 5046US5784579AMethod and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depthINTEL CORP·Filed 1996·Granted Jul 21, 1998·18 cites·11 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →