Inventor · disambiguated record
Gurbir Singh
Also filed as: SINGH GURBIR · SINGH GURBIR SINGH A L BALWANT
46 granted patents·3 pending applications·1,853 citations·filing 1987–2022
99Inventor score
Files withINTEL CORP30AGILENT TECHNOLOGIES INC5CADENCE DESIGN SYSTEMS INC3APTINA IMAGING CORP1AVAGO TECHNOLOGIES ECBU IP PTE1
Top patents by PatentIndex Score
49 records- 0197US6601121B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Jul 29, 2003·104 cites·23 claims
- 0296US6118306AChanging clock frequencyINTEL CORP·Filed 1999·Granted Sep 12, 2000·164 cites·35 claims
- 0391US6967321B2Optical navigation sensor with integrated lensAGILENT TECHNOLOGIES INC·Filed 2002·Granted Nov 22, 2005·75 cites·2 claims
- 0491USRE38388EMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 2001·Granted Jan 13, 2004·50 cites·73 claims
- 0591US5754833AMethod and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratioINTEL CORP·Filed 1997·Granted May 19, 1998·77 cites·22 claims
- 0689US7045775B2Optical navigation sensor with integrated lensAVAGO TECHNOLOGIES LTD·Filed 2005·Granted May 16, 2006·23 cites·13 claims
- 0785US6806583B2Light sourceAGILENT TECHNOLOGIES INC·Filed 2001·Granted Oct 19, 2004·49 cites·2 claims
- 0884US5581782AComputer system with distributed bus arbitration scheme for symmetric and priority agentsINTEL CORP·Filed 1995·Granted Dec 3, 1996·117 cites·48 claims
- 0983US6907487B2Enhanced highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Jun 14, 2005·22 cites·62 claims
- 1083US5615343AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1994·Granted Mar 25, 1997·69 cites·31 claims
- 1182US6804735B2Response and data phases in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Oct 12, 2004·21 cites·21 claims
- 1282US6006299AApparatus and method for caching lock conditions in a multi-processor systemINTEL CORP·Filed 1994·Granted Dec 21, 1999·94 cites·15 claims
- 1381US7836102B2Method and system for enhancing software documentation and help systemsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Nov 16, 2010·7 cites·31 claims
- 1480US5796977AHighly pipelined bus architectureINTEL CORP·Filed 1996·Granted Aug 18, 1998·89 cites·16 claims
- 1579US6880031B2Snoop phase in a highly pipelined bus architectureINTEL CORP·Filed 2001·Granted Apr 12, 2005·18 cites·22 claims
- 1678US7112916B2Light emitting diode based light source emitting collimated lightGOH KEE SIANG·Filed 2002·Granted Sep 26, 2006·36 cites·20 claims
- 1778US6807592B2Quad pumped bus architecture and protocolINTEL CORP·Filed 2001·Granted Oct 19, 2004·16 cites·25 claims
- 1877US5715428AApparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer systemINTEL CORP·Filed 1996·Granted Feb 3, 1998·82 cites·35 claims
- 1976US6202125B1Processor-cache protocol using simple commands to implement a range of cache configurationsINTEL CORP·Filed 1997·Granted Mar 13, 2001·83 cites·36 claims
- 2075US6879040B2Surface mountable electronic deviceAGILENT TECHNOLOGIES INC·Filed 2003·Granted Apr 12, 2005·20 cites·14 claims
- 2175US6768101B1High resolution optical encoder with an angular collimated light beamAGILENT TECHNOLOGIES INC·Filed 2003·Granted Jul 27, 2004·18 cites·13 claims
- 2272US5568620AMethod and apparatus for performing bus transactions in a computer systemINTEL CORP·Filed 1993·Granted Oct 22, 1996·58 cites·33 claims
- 2371US5903908AMethod and apparatus for maintaining cache coherency using a single controller for multiple cache memoriesINTEL CORP·Filed 1996·Granted May 11, 1999·60 cites·13 claims
- 2471US5832534AMethod and apparatus for maintaining cache coherency using a single controller for multiple cache memoriesINTEL CORP·Filed 1995·Granted Nov 3, 1998·43 cites·6 claims
- 2570US5809524AMethod and apparatus for cache memory replacement line identificationINTEL CORP·Filed 1997·Granted Sep 15, 1998·57 cites·16 claims
- 2670US4803622AProgrammable I/O sequencer for use in an I/O processorINTEL CORP·Filed 1987·Granted Feb 7, 1989·45 cites·3 claims
- 2769US6609171B1Quad pumped bus architecture and protocolINTEL CORP·Filed 1999·Granted Aug 19, 2003·34 cites·64 claims
- 2868US5345576AMicroprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache missINTEL CORP·Filed 1991·Granted Sep 6, 1994·54 cites·3 claims
- 2967US7358958B2Method for locating a light source relative to optics in an optical mouseAVAGO TECHNOLOGIES ECBU IP PTE·Filed 2004·Granted Apr 15, 2008·13 cites·15 claims
- 3063US7095621B2Leadless leadframe electronic package and sensor module incorporating sameAVAGO TECHNOLOGIES SENSOR IP S·Filed 2003·Granted Aug 22, 2006·10 cites·8 claims
- 3163US5678020AMemory subsystem wherein a single processor chip controls multiple cache memory chipsINTEL CORP·Filed 1996·Granted Oct 14, 1997·36 cites·24 claims
- 3260US7797353B1Method and system for enhancing software documentation and help systemsCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Sep 14, 2010·5 cites·42 claims
- 3360US5937171AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1996·Granted Aug 10, 1999·26 cites·43 claims
- 3458US5911053AMethod and apparatus for changing data transfer widths in a computer systemINTEL CORP·Filed 1996·Granted Jun 8, 1999·34 cites·14 claims
- 3556US7937418B2Method and system for enhancing software documentation and help systemsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted May 3, 2011·0 cites·36 claims
- 3656US5701503AMethod and apparatus for transferring information between a processor and a memory systemINTEL CORP·Filed 1994·Granted Dec 23, 1997·27 cites·22 claims
- 3754US6311281B1Apparatus and method for changing processor clock ratio settingsINTEL CORP·Filed 1999·Granted Oct 30, 2001·28 cites·20 claims
- 3853US7453516B2Flexible camera lens barrelAPTINA IMAGING CORP·Filed 2003·Granted Nov 18, 2008·5 cites·24 claims
- 3953US6242280B1Method of interconnecting an electronic deviceAGILENT TECHNOLOGIES INC·Filed 1999·Granted Jun 5, 2001·19 cites·10 claims
- 4051US5903738AMethod and apparatus for performing bus transactions in a computer systemINTEL CORP·Filed 1996·Granted May 11, 1999·24 cites·15 claims
- 4149US12314350B1Pay-per-use metering service for electronic design automation workloads in the cloudSYNOPSYS INC·Filed 2022·Granted May 27, 2025·0 cites·20 claims
- 4248US5923857AMethod and apparatus for ordering writeback data transfers on a busINTEL CORP·Filed 1996·Granted Jul 13, 1999·20 cites·15 claims
- 4346US6405271B1Data flow control mechanism for a bus supporting two-and three-agent transactionsINTEL CORP·Filed 1996·Granted Jun 11, 2002·12 cites·15 claims
- 4440US2006244113A1Leadless leadframe electronic package and sensor module incorporating sameSAIMUN LEE·Filed 2006·Application pending·0 cites
- 4539US5966722AMethod and apparatus for controlling multiple dice with a single dieINTEL CORP·Filed 1997·Granted Oct 12, 1999·9 cites·15 claims
- 4638US2004137656A1Low thermal resistance light emitting diode package and a method of making the sameFiled 2003·Application pending·0 cites
- 4736US11461353B2Identifying and extracting addresses within contentMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2018·Granted Oct 4, 2022·0 cites·15 claims
- 4835US2004217451A1Semiconductor packaging structureLEE SAI-MUN·Filed 2003·Application pending·0 cites
- 4930US7262493B2System and method for mounting electrical devicesAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Aug 28, 2007·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →