Inventor

PUNZALAN JEFFREY D

SG65 patents

⚠️ This page may combine multiple inventors who share the name “PUNZALAN JEFFREY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PUNZALAN JEFFREY D

STATS CHIPPAC LTD

Integrated circuit package system with leadframe array

Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die

Integrated circuit package system with interconnect support

Integrated circuit package system with heat sink

Integrated circuit package system with downset lead

Integrated circuit package-in-package system with leads

Multiple flip-chip integrated circuit package system

Integrated circuit package system with interconnection support and method of manufacture thereof

Multi-leadframe semiconductor package and method of manufacture

Integrated circuit package system with stiffener

Integrated circuit package system with heat sink

Large die package and method for the fabrication thereof

Integrated circuit package system with integral inner lead and paddle

Integrated circuit package system with leadfinger support

Integrated circuit package with elevated edge leadframe

Integrated circuit package system with multiple molding

Overhang integrated circuit package system

Integrated circuit package system with adhesive restraint

Wire-on-lead package system having leadfingers positioned between paddle extensions and method of manufacture thereof

Integrated circuit package system with different mold locking features

Non-leaded integrated circuit package system with multiple ground sites

Integrated circuit package system with laminate base

Integrated circuit package system with lead structures including a dummy tie bar

Integrated circuit package system with multiple device units

Integrated circuit package system with ground ring

Integrated circuit packaging system including a non-leaded package

Integrated circuit packaging system with base structure device

Integrated circuit leadless package system

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

ST ASSEMBLY TEST SERVICES LTD

Large die package structures and fabrication method therefor

Large die package structures and fabrication method therefor

Large die package structures and fabrication method therefor

Dual row leadframe and fabrication method

Dual row leadframe and fabrication method

Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor

Integrated circuit package with leadframe locked encapsulation and method of manufacture therefor

CAMACHO ZIGMUND RAMIREZ

Packaging system with hollow package and method for the same

Integrated circuit package system with die on base package

Integrated circuit package system

Integrated circuit package system including wide flange leadframe

Integrated circuit package system with laminate base

SHIM IL KWON

Integrated circuit package to package stacking system

Integrated circuit package system with relief

BATHAN HENRY DESCALZO

Integrated circuit package in package system with adhesiveless package attach

Integrated circuit packaging system with protective coating and method of manufacture thereof

PUNZALAN JEFFREY D

Integrated circuit package system with integral inner lead and paddle and method of manufacture thereof

Integrated circuit package system with flashless leads

CAMACHO ZIGMUND R

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

Semiconductor device with bump interconnection

ST ASSEMBLY TEST SERVICE LTD

Ground plane for exposed package