Inventor
MANOHARARAJAH VALAVAN
CA47 patents
⚠️ This page may combine multiple inventors who share the name “MANOHARARAJAH VALAVAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
36 patentsUS8677298B1Mar 18, 2014
Programmable device configuration methods adapted to account for retiming
ALTERA CORP18 citations92
US7500216B1Mar 3, 2009
Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines
ALTERA CORP42 citations92
US7360190B1Apr 15, 2008
Method and apparatus for performing retiming on field programmable gate arrays
ALTERA CORP25 citations92
US7290239B1Oct 30, 2007
Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays
ALTERA CORP18 citations91
US7257800B1Aug 14, 2007
Method and apparatus for performing logic replication in field programmable gate arrays
ALTERA CORP28 citations91
US9660650B1May 23, 2017
Integrated circuits with improved register circuitry
ALTERA CORP11 citations84
US9558849B1Jan 31, 2017
Methods for memory interface calibration
ALTERA CORP9 citations84
US9553590B1Jan 24, 2017
Configuring programmable integrated circuit device resources as processing elements
ALTERA CORP11 citations84
US8963581B1Feb 24, 2015
Pipelined direct drive routing fabric
ALTERA CORP8 citations84
US8863059B1Oct 14, 2014
Integrated circuit device configuration methods adapted to account for retiming
ALTERA CORP7 citations84
US8856702B1Oct 7, 2014
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP5 citations84
US7996797B1Aug 9, 2011
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP10 citations84
US7594204B1Sep 22, 2009
Method and apparatus for performing layout-driven optimizations on field programmable gate arrays
ALTERA CORP8 citations83
US7620925B1Nov 17, 2009
Method and apparatus for performing post-placement routability optimization
ALTERA CORP7 citations74
US10832787B2Nov 10, 2020
Methods for memory interface calibration
ALTERA CORP2 citations73
US8896344B1Nov 25, 2014
Heterogeneous programmable device and configuration software adapted therefor
ALTERA CORP4 citations73
US7565387B1Jul 21, 2009
Systems and methods for configuring a programmable logic device to perform a computation using carry chains
ALTERA CORP7 citations66
US10452392B1Oct 22, 2019
Configuring programmable integrated circuit device resources as processors
ALTERA CORP1 citations63
US9245085B2Jan 26, 2016
Integrated circuit device configuration methods adapted to account for retiming
ALTERA CORP2 citations63
US9030231B1May 12, 2015
Heterogeneous programmable device and configuration software adapted therefor
ALTERA CORP3 citations63
US7797666B1Sep 14, 2010
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
ALTERA CORP2 citations63
US7509597B1Mar 24, 2009
Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams
ALTERA CORP5 citations63
US7444613B1Oct 28, 2008
Systems and methods for mapping arbitrary logic functions into synchronous embedded memories
ALTERA CORP4 citations63
US8904318B1Dec 2, 2014
Method and apparatus for performing optimization using don't care states
ALTERA CORP3 citations60
US7412677B1Aug 12, 2008
Detecting reducible registers
ALTERA CORP5 citations60
US10572224B2Feb 25, 2020
Methods and apparatus for sequencing multiply-accumulate operations
ALTERA CORP0 citations52
US10332612B2Jun 25, 2019
Methods for memory interface calibration
ALTERA CORP0 citations52
US10037396B2Jul 31, 2018
Integrated circuit device configuration methods adapted to account for retiming
ALTERA CORP0 citations52
US10019234B2Jul 10, 2018
Methods and apparatus for sequencing multiply-accumulate operations
ALTERA CORP1 citations52
US9911506B1Mar 6, 2018
Methods for memory interface calibration
ALTERA CORP0 citations52
US9589090B1Mar 7, 2017
Method and apparatus for performing multiple stage physical synthesis
ALTERA CORP0 citations52
US9401718B1Jul 26, 2016
Heterogeneous programmable device and configuration software adapted therefor
ALTERA CORP0 citations52
US9360884B2Jun 7, 2016
Clocking for pipelined routing
ALTERA CORP1 citations52
US9100011B1Aug 4, 2015
Pipelined direct drive routing fabric
ALTERA CORP0 citations52
US8839172B1Sep 16, 2014
Specification of latency in programmable device configuration
ALTERA CORP0 citations52
US8645885B1Feb 4, 2014
Specification of multithreading in programmable device configuration
ALTERA CORP1 citations52
MANOHARARAJAH VALAVAN
4 patentsUS8565033B1Oct 22, 2013
Methods for calibrating memory interface circuitry
MANOHARARAJAH VALAVAN79 citations96
US8201114B1Jun 12, 2012
Method and apparatus for performing look up table unpacking and repacking for resynthesis
MANOHARARAJAH VALAVAN7 citations82
US8578306B2Nov 5, 2013
Method and apparatus for performing asynchronous and synchronous reset removal during synthesis
MANOHARARAJAH VALAVAN2 citations62
US8847624B1Sep 30, 2014
Method and system for operating a circuit
MANOHARARAJAH VALAVAN0 citations41