Methods for memory interface calibration

Abstract

Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability density function curves as a function of timing window edge asymmetry for different degrees of oversampling. During calibration, duty cycle distortion in data strobe signals may be corrected by selectively delaying the data strobe rising or falling edges. A data clock signal that is used for generating data signals may also suffer from duty cycle distortion. The rising and falling edges of the data clock signal may be selectively delayed to correct for duty cycle distortion. The data path through which the data signals are routed may be adjusted to equalize rising and falling transitions to minimize data path duty cycle distortion. Multi-rank calibration may be performed by calibrating to an intersection of successful settings that allow each memory rank to pass memory operation tests.

What is claimed is: 
     
       1. A system, comprising:
 a memory device, wherein the memory device comprises two or more memory ranks; and 
 a field programmable gate array, comprising memory interface circuitry configured to facilitate data communication between a programmable logic circuit of the field programmable gate array and the memory device and configured to:
 perform a calibration test on the two or more memory ranks; 
 determine, for the two or more memory ranks, a range of timing settings for operating a respective memory rank based at least in part on the calibration test; 
 determine a common timing setting that is among the range of timing settings; and 
 configure the memory interface circuitry using the common timing setting. 
 
 
     
     
       2. The system of  claim 1 , wherein the memory interface circuitry comprises a memory controller, memory interface calibration circuitry, a memory interface circuit, or any combination thereof. 
     
     
       3. The system of  claim 1 , wherein the field programmable gate array comprises a processor configured to communicate with the memory device via the memory interface circuitry. 
     
     
       4. The system of  claim 1 , wherein the memory device is configured to communicate via a double data rate protocol. 
     
     
       5. The system of  claim 1 , wherein the memory interface circuitry is configured to communicate data signals and data strobe signals to the memory device, and wherein the memory interface circuitry is configured to, using the common timing setting, center the data strobe signals relative to the data signals. 
     
     
       6. The system of  claim 1 , comprising:
 a first control path configured to convey first test data between the memory interface circuitry and a first memory rank in the two or more memory ranks, wherein the range of timing settings is determined based at least in part on the first test data; and 
 a second control path configured to convey second test data between the memory interface circuitry and a second memory rank in the two or more memory ranks, wherein the range of timing settings is determined based at least in part on the second test data. 
 
     
     
       7. The system of  claim 6 , wherein the first test data comprises one or more test measurements corresponding to the calibration test, and wherein performing the calibration test comprises oversampling the test measurements using a predetermined oversampling factor. 
     
     
       8. The system of  claim 1 , wherein the memory device comprises a memory module, and wherein the memory module comprises the two or more memory ranks. 
     
     
       9. The system of  claim 1 , wherein the memory device comprises a first memory module and a second memory module, and wherein the first memory module comprises one or more of the two or more memory ranks and the second memory module comprises an additional one or more of the two or more memory ranks. 
     
     
       10. The system of  claim 1 , wherein the calibration test comprises a read test. 
     
     
       11. The system of  claim 1 , wherein the field programmable gate array is configured to:
 perform the calibration test on the two or more memory ranks at least in part by:
 performing, using the memory interface circuitry configured to facilitate data communication between the programmable logic circuit of the field programmable gate array and the memory device, a first calibration test of a first memory rank of the two or more memory ranks; and 
 performing, using the memory interface circuitry, a second calibration test of a second memory rank of the two or more memory ranks, wherein the memory interface circuitry is configured to perform the second calibration test separately from the first calibration test; 
 
 determine, for the two or more memory ranks, the range of timing settings for operating the respective rank at least in part by:
 determining a first range of settings for operating the first memory rank based at least in part on the first calibration test; and 
 determining a second range of settings for operating the second memory rank based at least in part on the second calibration test; 
 
 determine the common timing setting that is among the range of timing settings at least in part by determining the common timing setting that is among the first range of settings and the second range of settings; and 
 operate the memory interface circuitry using the common timing setting.