Inventor · disambiguated record
Ryan Fung
Also filed as: FUNG RYAN
76 granted patents·5 pending applications·681 citations·filing 2002–2020
99Inventor score
Top patents by PatentIndex Score
81 records- 0198US8588014B1Methods for memory interface calibrationFUNG RYAN·Filed 2011·Granted Nov 19, 2013·36 cites·12 claims
- 0297US8565033B1Methods for calibrating memory interface circuitryMANOHARARAJAH VALAVAN·Filed 2011·Granted Oct 22, 2013·79 cites·20 claims
- 0395US9569574B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2014·Granted Feb 14, 2017·35 cites·19 claims
- 0495US8775701B1Method and apparatus for source-synchronous capture using a first-in-first-out unitFUNG RYAN·Filed 2011·Granted Jul 8, 2014·25 cites·25 claims
- 0594US8281274B1Method and apparatus for performing efficient incremental compilationPADALIA KETAN·Filed 2010·Granted Oct 2, 2012·23 cites·40 claims
- 0692US9558849B1Methods for memory interface calibrationALTERA CORP·Filed 2013·Granted Jan 31, 2017·9 cites·20 claims
- 0792US8677298B1Programmable device configuration methods adapted to account for retimingALTERA CORP·Filed 2013·Granted Mar 18, 2014·18 cites·26 claims
- 0891US9275178B1Method and apparatus for considering paths influenced by different power supply domains in timing analysisALTERA CORP·Filed 2012·Granted Mar 1, 2016·14 cites·26 claims
- 0989US8539418B1Method and apparatus for performing efficient incremental compilationPADALIA KETAN·Filed 2012·Granted Sep 17, 2013·10 cites·24 claims
- 1089US8255860B1Exploiting independent portions of logic designs for timing optimizationFUNG RYAN·Filed 2010·Granted Aug 28, 2012·13 cites·24 claims
- 1189US7712067B1Method and apparatus for facilitating effective and efficient optimization of short-path timing constraintsALTERA CORP·Filed 2007·Granted May 4, 2010·18 cites·32 claims
- 1289US7676768B1Automatic asynchronous signal pipeliningALTERA CORP·Filed 2006·Granted Mar 9, 2010·13 cites·16 claims
- 1387US11093672B2Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2020·Granted Aug 17, 2021·2 cites·19 claims
- 1487US7853911B1Method and apparatus for performing path-level skew optimization and analysis for a logic designALTERA CORP·Filed 2005·Granted Dec 14, 2010·15 cites·36 claims
- 1586US8929162B1Gating and sampling a data strobe signal using a shared enable signalFENDER JOSHUA DAVID·Filed 2012·Granted Jan 6, 2015·10 cites·18 claims
- 1686US8863059B1Integrated circuit device configuration methods adapted to account for retimingALTERA CORP·Filed 2013·Granted Oct 14, 2014·7 cites·24 claims
- 1786US7911240B1Clock switch-over circuits and methodsALTERA CORP·Filed 2007·Granted Mar 22, 2011·14 cites·22 claims
- 1886US7737751B1Periphery clock distribution network for a programmable logic deviceALTERA CORP·Filed 2007·Granted Jun 15, 2010·16 cites·44 claims
- 1986US6871328B1Method for mapping logic design memory into physical memory device of a programmable logic deviceALTERA CORP·Filed 2002·Granted Mar 22, 2005·39 cites·77 claims
- 2084US8261218B1Systems and methods for determining beneficial clock-path connection delaysFUNG RYAN·Filed 2009·Granted Sep 4, 2012·13 cites·39 claims
- 2184US7138844B2Variable delay circuitryALTERA CORP·Filed 2005·Granted Nov 21, 2006·13 cites·21 claims
- 2283US8949763B1Apparatus and methods for optimization of integrated circuitsFUNG RYAN·Filed 2008·Granted Feb 3, 2015·10 cites·12 claims
- 2383US7370291B2Method for mapping logic design memory into physical memory devices of a programmable logic deviceALTERA CORP·Filed 2005·Granted May 6, 2008·11 cites·66 claims
- 2482US7977975B1Apparatus for using metastability-hardened storage circuits in logic devices and associated methodsALTERA CORP·Filed 2009·Granted Jul 12, 2011·8 cites·28 claims
- 2582US7788614B1Method and apparatus for performing analytic placement techniques on logic devices with restrictive areasALTERA CORP·Filed 2007·Granted Aug 31, 2010·12 cites·34 claims
- 2681US9697309B1Metastability-hardened synchronization circuitFUNG RYAN·Filed 2009·Granted Jul 4, 2017·10 cites·22 claims
- 2781US8898609B1Method and apparatus for integrating signal transition time modeling during routingGOUTERMAN VADIM·Filed 2006·Granted Nov 25, 2014·15 cites·34 claims
- 2881US8732639B1Method and apparatus for protecting, optimizing, and reporting synchronizersFUNG RYAN·Filed 2009·Granted May 20, 2014·9 cites·37 claims
- 2981US8572530B1Method and apparatus for performing path-level skew optimization and analysis for a logic designFUNG RYAN·Filed 2010·Granted Oct 29, 2013·5 cites·21 claims
- 3080US8904331B1Method and apparatus for performing time domain jitter modelingFUNG RYAN·Filed 2012·Granted Dec 2, 2014·5 cites·23 claims
- 3179US10832787B2Methods for memory interface calibrationALTERA CORP·Filed 2019·Granted Nov 10, 2020·2 cites·11 claims
- 3279US8402416B1Method and apparatus for composing and decomposing low-skew networksFUNG RYAN·Filed 2011·Granted Mar 19, 2013·4 cites·16 claims
- 3379US7207020B1Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation toolALTERA CORP·Filed 2004·Granted Apr 17, 2007·21 cites·49 claims
- 3478US8232826B1Techniques for multiplexing delayed signalsNGUYEN ANDY·Filed 2010·Granted Jul 31, 2012·5 cites·27 claims
- 3578US7694256B1Method and apparatus for performing analytic placement techniques on logic devices with restrictive areasALTERA CORP·Filed 2007·Granted Apr 6, 2010·9 cites·22 claims
- 3677US9166570B2Apparatus for using metastability-hardened storage circuits in logic devices and associated methodsALTERA CORP·Filed 2013·Granted Oct 20, 2015·3 cites·20 claims
- 3777US7290232B1Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variabilityALTERA CORP·Filed 2004·Granted Oct 30, 2007·20 cites·29 claims
- 3875US9594859B1Apparatus and associated methods for parallelizing clustering and placementPADALIA KETAN·Filed 2008·Granted Mar 14, 2017·8 cites·33 claims
- 3975US8930597B1Method and apparatus for supporting low-latency external memory interfaces for integrated circuitsFUNG RYAN·Filed 2011·Granted Jan 6, 2015·6 cites·29 claims
- 4074US9792458B2Platform to build secure mobile collaborative applications using dynamic presentation and data configurationsIMS HEALTH INCORPORATED·Filed 2014·Granted Oct 17, 2017·5 cites·20 claims
- 4174US9245085B2Integrated circuit device configuration methods adapted to account for retimingALTERA CORP·Filed 2014·Granted Jan 26, 2016·2 cites·24 claims
- 4274US8930175B1Method and apparatus for performing timing analysis that accounts for rise/fall skewFUNG RYAN·Filed 2012·Granted Jan 6, 2015·3 cites·25 claims
- 4374US7629825B1Efficient delay elementsALTERA CORP·Filed 2006·Granted Dec 8, 2009·6 cites·11 claims
- 4473US7257795B1Method and apparatus for facilitating effective and efficient optimization of short-path timing constraintsALTERA CORP·Filed 2004·Granted Aug 14, 2007·14 cites·34 claims
- 4572US9722794B2System and method for remote access, remote digital signatureIMS HEALTH INCORPORATED·Filed 2014·Granted Aug 1, 2017·4 cites·20 claims
- 4672US7958466B1Method and apparatus for calculating a scalar quality metric for quantifying the quality of a design solutionALTERA CORP·Filed 2006·Granted Jun 7, 2011·5 cites·48 claims
- 4772US7308664B1Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routingALTERA CORP·Filed 2004·Granted Dec 11, 2007·14 cites·60 claims
- 4871US10635772B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2016·Granted Apr 28, 2020·1 cites·8 claims
- 4970US8508254B2Apparatus for using metastability-hardened storage circuits in logic devices and associated methodsLEWIS DAVID·Filed 2011·Granted Aug 13, 2013·2 cites·20 claims
- 5070US2021082534A1Methods for memory interface calibrationALTERA CORP·Filed 2020·Application pending·0 cites
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →